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PDF 80960JA Data sheet ( Hoja de datos )
| Número de pieza | 80960JA | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR | |
| Fabricantes | Intel Corporation | |
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A
PRELIMINARY
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
Processors
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
s Two-Way Set Associative Instruction Cache s High-Speed Interrupt Controller
— 80960JA - 2 Kbyte
— 80960JF - 4 Kbyte
— Programmable Cache Locking
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JA - 1 Kbyte
— 80960JF - 2 Kbyte
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
— Write Through Operation
s Halt Mode for Low Power
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
— 0-7 Frames Reserved for High-Priority s Packages
Interrupts
— 132-Lead Pin Grid Array (PGA)
s On-Chip Data RAM
— 132-Lead Plastic Quad Flat Pack (PQFP)
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
iA80960Jx
XXXXXXXXA2
M © 19xx
PIN 1
132
33
A
i960®
iNG80960Jx
XXXXXXXXA2
M © 19xx
99
66
Figure 1. 80960JA/JF Microprocessors
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272504-004
1 page  
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A
80960JA/JF
1.0 PURPOSE
This document contains preliminary information for
the 80960JA/JF microprocessor, including electrical
characteristics and package pinout information.
Detailed functional descriptions — other than
parametric performance — are published in the
i960® Jx Microprocessor User’s Guide (272483).
Throughout this data sheet, references to “80960Jx”
indicate features which apply to all of the following:
• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte
data cache
• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache
• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache and clock doubling
• 80L960JA — 3.3 V version of the 80960JA
• 80L960JF — 3.3 V version of the 80960JF
2.0 80960JA/JF OVERVIEW
The 80960JA/JF offers high performance to cost-
sensitive 32-bit embedded applications. The
80960JA/JF is object code compatible with the
80960 Core Architecture and is capable of sustained
execution at the rate of one instruction per clock.
This processor’s features include generous
instruction cache, data cache and data RAM. It also
boasts a fast interrupt mechanism, dual program-
mable timer units and new instructions.
Memory subsystems for cost-sensitive embedded
applications often impose substantial wait state
penalties. The 80960JA/JF integrates considerable
storage resources on-chip to decouple CPU
execution from the external bus.
The 80960JA/JF rapidly allocates and deallocates
local register sets during context switches. The
processor needs to flush a register set to the stack
only when it saves more than seven sets to its local
register cache.
A 32-bit multiplexed burst bus provides a high-speed
interface to system memory and I/O. A full
complement of control signals simplifies the
connection of the 80960JA/JF to external compo-
nents. The user programs physical and logical
memory attributes through memory-mapped control
registers (MMRs) — an extension not found on the
i960 Kx, Sx or Cx processors. Physical and logical
configuration registers enable the processor to
operate with all combinations of bus width and data
object alignment. The processor supports a homoge-
neous byte ordering model.
This processor integrates two important peripherals:
a timer unit and an interrupt controller. These and
other hardware resources are programmed through
memory-mapped control registers, an extension to
the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit
timers for use as real-time system clocks and
general-purpose system timing. These operate in
either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible,
low-latency means for requesting interrupts.The ICU
provides full programmability of up to 240 interrupt
sources into 31 priority levels. The ICU takes
advantage of a cached priority table and optional
routine caching to minimize interrupt latency. Local
registers may be dedicated to high-priority interrupts
to further reduce latency. Acting independently from
the core, the ICU compares the priorities of posted
interrupts with the current process priority, off-
loading this task from the core. The ICU also
supports the integrated timer interrupts.
The 80960JA/JF features a Halt mode designed to
support applications where low power consumption
is critical. The halt instruction shuts down instruction
execution, resulting in a power savings of up to 90
percent.
The 80960JA/JF’s testability features, including
ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for
design debug and fault diagnosis.
The Solutions960® program features a wide variety
of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For
more information on these products, contact your
local Intel representative.
PRELIMINARY
1
5 Page 
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A
80960JA/JF
NAME
AD31:0
ALE
ALE
ADS
A3:2
Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)
TYPE
I/O
S(L)
R(X)
H(Z)
P(Q)
O
R(0)
H(Z)
P(0)
O
R(1)
H(Z)
P(1)
O
R(1)
H(Z)
P(1)
O
R(X)
H(Z)
P(Q)
DESCRIPTION
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (Ta) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the
number of data transfers during the bus transaction.
AD1 AD0
Bus Transfers
00
01
10
11
1 Transfer
2 Transfers
3 Transfers
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active HIGH and floats to a high impedance state during a hold cycle (Th).
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960JA/JF a high degree of compat-
ibility with existing 80960Kx systems.
ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire Ta cycle. External bus control logic typically
samples ADS at the end of the cycle.
ADDRESS3:2 comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A3:2 during Ta. The
partial word address increments with each assertion of RDYRCV during a burst.
16-bit memory accesses: the processor asserts address bits A3:1 during Ta with A1
driven on the BE1 pin. The partial short word address increments with each
assertion of RDYRCV during a burst.
8-bit memory accesses: the processor asserts address bits A3:0 during Ta, with A1:0
driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.
PRELIMINARY
7
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