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82C50 PDF даташит

Спецификация 82C50 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Asynchronous Communications Element».

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Номер произв 82C50
Описание CMOS Asynchronous Communications Element
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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82C50 Даташит, Описание, Даташиты
82C50A
March 1997
CMOS Asynchronous
Communications Element
Features
• Single Chip UART/BRG
• DC to 625K Baud (DC to 10MHz Clock)
• Crystal or External Clock Input
• On Chip Baud Rate Generator 1 to 65535 Divisor
Generates 16X Clock
• Prioritized Interrupt Mode
• Fully TTL/CMOS Compatible
• Microprocessor Bus Oriented Interface
• 80C86/80C88 Compatible
• Scaled SAJI IV CMOS Process
• Low Power - 1mA/MHz Typical
• Modem Interface
• Line Break Generation and Detection
• Loopback and Echo Modes
• Doubled Buffered Transmitter and Receiver
• Single 5V Supply
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
TEMPERATURE
RANGE (oC)
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
-55 to +125
625K BAUD
CP82C50A-5
IP82C50A-5
CS82C50A-5
IS82C50A-5
CD82C50A-5
ID82C50A-5
MD82C50A-5/B
PKG.
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
Description
The 82C50A Asynchronous Communication Element (ACE)
is a high performance programmable Universal Asynchro-
nous Receiver/Transmitter (UART) and Baud Rate Genera-
tor (BRG) on a single chip. Using Intersil’s advanced Scaled
SAJI IV CMOS Process, the ACE will support data rates
from DC to 625K baud (0-10MHz clock).
The ACE’s receiver circuitry converts start, data, stop, and
parity bits into a parallel data word. The transmitter circuitry
converts a parallel data word into serial form and appends
the start, parity, and stop bits. The word length is program-
mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a
choice of 1,1.5, or 2 stop bits.
The Baud Rate Generator divides the clock by a divisor
programmable from 1 to 216-1 to provide standard RS-232C
baud rates when using any one of three industry standard
baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (BAUDOUT) provides
either a buffered oscillator or 16X (16 times the data rate)
baud rate clock for general purpose system use.
To meet the system requirements of a CPU interfacing to an
asynchronous channel, the modem control signals RTS,
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs
have been designed with full TTL/CMOS compatibility in
order to facilitate mixed TTL/NMOS/CMOS system design.
Functional Diagram
CSO
CS1
CS2
12
13
14
ADS 25
A0 28
A1 27
A2 26
MR 35
DISTR 22
DISTR 21
DOSTR 19
DOSTR 18
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
MICROPROCESSOR INTERFACE
24 CSOUT
23 DDIS
INTERRUPT 30 INTRPT
ENABLE,
ID, & CONTROL
UART
RECEIVER
LINE STATUS DIVISOR LATCH
AND CONTROL AND BAUD RATE
GENERATOR
TRANSMITTER
MODEM
MODEM CONTROL
MODEM STATUS
10 SIN
9 RCLK
15 BAUDOUT
16 XTAL1
17 XTAL2
11 SOUT
32 RTS
33 DTR
34 OUT1
31 OUT2
36 CTS
37 DSR
38 DCD
39 RI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2958.1









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82C50 Даташит, Описание, Даташиты
Pinouts
82C50A
82C50A (PDIP, CERDIP)
TOP VIEW
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XTAL1
XTAL2
DOSTR
DOSTR
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 RI
38 DCD
37 DSR
36 CTS
35 MR
34 OUT1
33 DTR
32 RTS
31 OUT2
30 INTRPT
29 NC
28 A0
27 A1
26 A2
25 ADS
24 CSOUT
23 DDIS
22 DISTR
21 DISTR
82C50A (PLCC)
TOP VIEW
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRP
NC
A0
A1
A2
2









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82C50 Даташит, Описание, Даташиты
82C50A
Pin Description
PIN
SYMBOL NUMBER
DISTR,
DISTR
22
21
TYPE
I
I
DOSTR,
DOSTR
19
18
I
I
D0-D7
1-8
I/O
A0, A1,
A2
XTAL1,
XTAL2
28, 27,
26
16
17
SOUT
11
I
I
I
O
O
GND
CTS
20
36
I
DSR
37
I
DTR
33
O
ACTIVE
LEVEL
DESCRIPTION
H DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause
L the 82C50A to output data to the data bus (D0-D7). The data output depends upon
the register selected by the address inputs A0, A1, A2. The chip select inputs CS0,
CS1, CS2 enable the DISTR, DISTR inputs.
Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A
during a read operation. If DISTR is used as the read input, DlSTR should be tied
high. If DISTR is used as the active read input, DISTR should be tied low.
H DATA OUT STROBE, DATA OUT STROBE: DOSTR, DOSTR are write inputs which
L cause data from the data bus (D0-D7) to be input to the 82C50A. The data input de-
pends upon the register selected by the address inputs A0, A1, A2. The chip select
inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs.
Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A
during a write operation. If DOSTR is used as the write input, DOSTR should be tied
high. If DOSTR is used as the write input, DOSTR should be tied low.
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the
transfer of data, control and status information between the 82C50A and the CPU.
For character formats of less than 8 bits, D7, D6 and D5 are “don’t cares” for data
write operations and 0 for data read operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB)
and is the first serial data bit to be received or transmitted.
H REGISTER SELECT: The address lines select the internal registers during CPU
bus operations. See Table 1.
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator.
XTAL1 can also be used as an external clock input, in which case XTAL2 should be
left open.
SERIAL DATA OUTPUT: Serial data output from the 82C50A transmitter circuitry. A
Mark (1) is a logic one (high) and Space (0) is a logic zero (low). SOUT is held in the
Mark condition when the transmitter is disabled, MR is true, the Transmitter Register
is empty, or when in the Loop Mode. SOUT is not affected by the CTS input.
L GROUND: Power supply ground connection (VSS).
L CLEAR TO SEND: The logical state of the CTS pin is reflected in the CTS bit of the
(MSR) Modem Status Register (CTS is bit 4 of the MSR, written MSR (4)). A change
of state in the CTS pin since the previous reading of the MSR causes the setting of
DCTS (MSR(O)) of the Modem Status Register. When CTS pin is ACTIVE (low), the
modem is indicating that data on SOUT can be transmitted on the communications
link. If CTS pin goes INACTIVE (high), the 82C50A should not be allowed to transmit
data out of SOUT. CTS pin does not affect Loop Mode operation.
L DATA SET READY: The logical state of the DSR pin is reflected in MSR(5) of the
Modem Status Register. DDSR (MSR(1)) indicates whether the DSR pin has
changed state since the previous reading of the MSR. When the DSR pin is ACTIVE
(low), the modem is indicating that it is ready to exchange data with the 82C50A,
while the DSR Pin INACTIVE (high) indicates that the modem is not ready for data
exchange. The ACTIVE condition indicates only the condition of the local Data Com-
munications Equipment (DCE), and does not imply that a data circuit as been estab-
lished with remote equipment.
L DATA TERMINAL READY: The DTR pin can be set (low) by writing a logic 1 to
MCR(0), Modem Control Register bit 0. This signal is cleared (high) by writing a logic
0 to the DTR bit (MCR(0)) or whenever a MR ACTIVE (high) is applied to the
82C50A. When ACTIVE (low), DTR pin indicates to the DCE that the 82C50A is
ready to receive data. In some instances, DTR pin is used as a power on indicator.
The INACTIVE (high) state causes the DCE to disconnect the modem from the tele-
communications circuit.
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