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82C55 PDF даташит

Спецификация 82C55 изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «CHMOS PROGRAMMABLE PERIPHERAL INTERFACE».

Детали детали

Номер произв 82C55
Описание CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Производители Intel Corporation
логотип Intel Corporation логотип 

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82C55 Даташит, Описание, Даташиты
82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y Compatible with all Intel and Most
Other Microprocessors
Y High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Y 24 Programmable I O Pins
Y Low Power CHMOS
Y Completely TTL Compatible
Y Control Word Read-Back Capability
Y Direct Bit Set Reset Capability
Y 2 5 mA DC Drive Capability on all I O
Port Outputs
Y Available in 40-Pin DIP and 44-Pin PLCC
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
The Intel 82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose
programmable I O device which is designed for use with all Intel and most other microprocessors It provides
24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5
In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In
MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used
for handshaking and interrupt control signals MODE 2 is a strobed bi-directional bus configuration
The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages
231256 – 31
Figure 1 82C55A Block Diagram
231256 – 1
231256 – 2
Figure 2 82C55A Pinout
Diagrams are for pin reference only Package
sizes are not to scale
October 1995
Order Number 231256-004









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82C55 Даташит, Описание, Даташиты
82C55A
Symbol
PA3 – 0
RD
CS
GND
A1 – 0
PC7 – 4
PC0 – 3
PB0-7
VCC
D7 – 0
RESET
WR
PA7 – 4
NC
Pin Number
Dip PLCC
1–4 2–5
56
67
78
8– 9 9–10
10– 13 11 13–15
14– 17
18– 25
26
27– 34
35
16 – 19
20 – 22
24 – 28
29
30 – 33
35 – 38
39
36 40
37– 40 41–44
1 12
23 34
Table 1 Pin Description
Type
Name and Function
I O PORT A PINS 0 – 3 Lower nibble of an 8-bit data output latch
buffer and an 8-bit data input latch
I READ CONTROL This input is low during CPU read operations
I CHIP SELECT A low on this input enables the 82C55A to
respond to RD and WR signals RD and WR are ignored
otherwise
System Ground
I ADDRESS These input signals in conjunction RD and WR
control the selection of one of the three ports or the control
word registers
A1 A0 RD WR CS Input Operation (Read)
00010
Port A - Data Bus
01010
Port B - Data Bus
10010
Port C - Data Bus
1 1 0 1 0 Control Word - Data Bus
Output Operation (Write)
00100
Data Bus - Port A
01100
Data Bus - Port B
10100
Data Bus - Port C
11100
Data Bus - Control
Disable Function
XXXX1
Data Bus - 3 - State
XX1 1 0
Data Bus - 3 - State
I O PORT C PINS 4 – 7 Upper nibble of an 8-bit data output latch
buffer and an 8-bit data input buffer (no latch for input) This port
can be divided into two 4-bit ports under the mode control Each
4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports
A and B
I O PORT C PINS 0 – 3 Lower nibble of Port C
I O PORT B PINS 0 – 7 An 8-bit data output latch buffer and an 8-
bit data input buffer
SYSTEM POWER a 5V Power Supply
I O DATA BUS Bi-directional tri-state data bus lines connected to
system data bus
I RESET A high on this input clears the control register and all
ports are set to the input mode
I WRITE CONTROL This input is low during CPU write
operations
I O PORT A PINS 4 – 7 Upper nibble of an 8-bit data output latch
buffer and an 8-bit data input latch
No Connect
2









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82C55 Даташит, Описание, Даташиты
82C55A
82C55A FUNCTIONAL DESCRIPTION
General
The 82C55A is a programmable peripheral interface
device designed for use in Intel microcomputer sys-
tems Its function is that of a general purpose I O
component to interface peripheral equipment to the
microcomputer system bus The functional configu-
ration of the 82C55A is programmed by the system
software so that normally no external logic is neces-
sary to interface peripheral devices or structures
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to inter-
face the 82C55A to the system data bus Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU Control
words and status information are also transferred
through the data bus buffer
Read Write and Control Logic
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words It accepts inputs from the
CPU Address and Control busses and in turn issues
commands to both of the Control Groups
Group A and Group B Controls
The functional configuration of each port is pro-
grammed by the systems software In essence the
CPU ‘‘outputs’’ a control word to the 82C55A The
control word contains information such as ‘‘mode’’
‘‘bit set’’ ‘‘bit reset’’ etc that initializes the func-
tional configuration of the 82C55A
Each of the Control blocks (Group A and Group B)
accepts ‘‘commands’’ from the Read Write Control
Logic receives ‘‘control words’’ from the internal
data bus and issues the proper commands to its as-
sociated ports
Control Group A - Port A and Port C upper (C7 – C4)
Control Group B - Port B and Port C lower (C3 – C0)
The control word register can be both written and
read as shown in the address decode table in the
pin descriptions Figure 6 shows the control word
format for both Read and Write operations When
the control word is read bit D7 will always be a logic
‘‘1’’ as this implies control word mode information
Ports A B and C
The 82C55A contains three 8-bit ports (A B and C)
All can be configured in a wide variety of functional
characteristics by the system software but each has
its own special features or ‘‘personality’’ to further
enhance the power and flexibility of the 82C55A
Port A One 8-bit data output latch buffer and one
8-bit input latch buffer Both ‘‘pull-up’’ and ‘‘pull-
down’’ bus hold devices are present on Port A
Port B One 8-bit data input output latch buffer
Only ‘‘pull-up’’ bus hold devices are present on Port
B
Port C One 8-bit data output latch buffer and one
8-bit data input buffer (no latch for input) This port
can be divided into two 4-bit ports under the mode
control Each 4-bit port contains a 4-bit latch and it
can be used for the control signal outputs and status
signal inputs in conjunction with ports A and B Only
‘‘pull-up’’ bus hold devices are present on Port C
See Figure 4 for the bus-hold circuit configuration for
Port A B and C
3










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