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PDF 82C55A Data sheet ( Hoja de datos )

Número de pieza 82C55A
Descripción CMOS Programmable Peripheral Interface
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82C55A datasheet


1. - CMOS Programmable Peripheral Interface






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Data Sheet
December 8, 2015
82C55A
FN2969.11
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A
Ordering Information
PART NUMBERS
5MHz
PART
MARKING
8MHz
PART
MARKING
CP82C55A-5
(No longer available,
recommended
replacement:
CP82C55A-5Z)
CP82C55A-5
CP82C55A
CP82C55A
CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ
IP82C55A
IP82C55A
IP82C55AZ (Note) IP82C55AZ
CS82C55A-5*
(No longer available,
recommended
replacement:
CS82C55A-5Z)
CS82C55A-5
CS82C55A*
CS82C55A*
CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ
IS82C55A-5*
IS82C55A-5 IS82C55A*
IS82C55A*
IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ
CQ82C55AZ (Note) CQ82C55AZ
IQ82C55AZ* (Note) IQ82C55AZ
ID82C55A
ID82C55A
MD82C55A/B
MD82C55A/B
8406602QA
8406602QA
8406602XA
8406602XA
*Add “96” suffix to part number for tape and reel packaging.
TEMP.
RANGE (°C)
0 to +70
PACKAGE
40 Ld PDIP
0 to +70
-40 to +85
-40 to +85
0 to +70
40 Ld PDIP (Pb-free)
40 Ld PDIP
40 Ld PDIP (Pb-free)
44 Ld PLCC
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
-55 to +125
SMD#
SMD#
44 Ld PLCC (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld MQFP (Pb-free)
44 Ld MQFP (Pb-free)
40 Ld CERDIP
44 Ld CLCC
PKG. DWG. #
E40.6
N44.65
Q44.10x10
F40.6
J44.A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2005, 2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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82C55A pdf
82C55A
two 4-bit ports under the mode control. Each 4-bit port
contains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
MASTER
RESET
OR MODE
CHANGE
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
INPUT MODE
EXTERNAL
PORT A PIN
OUTPUT MODE
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
RESET
OR MODE
CHANGE
VCC
P
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
EXTERNAL
PORT B, C
PIN
OUTPUT MODE
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
Operational Description
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need to pull-up or
pull-down resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
ADDRESS BUS
CONTROL BUS
DATA BUS
RD, WR
MODE 0
B
D7-D0
82C55A
C
A0-A1
CS
A
8 I/O 4 I/O 4 I/O 8 I/O
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
MODE 1
C
BA
8 I/O
8 I/O
MODE 2
PB7-PB0 CONTROL CONTROL PA7-PA0
OR I/O OR I/O
B
8 I/O
C
A
BI-
DIRECTIONAL
PB7-PB0
CONTROL
PA7-PA0
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
5 FN2969.11
December 8, 2015

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82C55A arduino
WR
OBF
INTR
ACK
OUTPUT
82C55A
tWOB
tAOB
tWIT
tAK
tWB
FIGURE 9. MODE 1 (STROBED OUTPUT)
tAIT
PA7-PA0 8
PA7-PA0 8
RD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0 1 0
PC6, PC7
1 = INPUT
0 = OUTPUT
PC4
PC5
PC3
PC6, PC7
PB7, PB0
STBA
IIBFA
INTRA
2
I/O
8
WR
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0 1 1
PC4, PC5
1 = INPUT
0 = OUTPUT
PC7
PC6
PC3
PC4, PC5
PB7, PB0
OBFA
ACKA
INTRA
2
I/O
8
WR
PC1
OBFB
PC2
ACKB
PC0
INTRB
RD
PC2
STBB
PC1
IBFB
PC0
INTRB
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bidirectional bus Port (Port A) and a 5-bit
control Port (Port C)
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A)
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
Output Operations
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
11 FN2969.11
December 8, 2015

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