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82C83H PDF даташит

Спецификация 82C83H изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Octal Latching Inverting Bus Driver».

Детали детали

Номер произв 82C83H
Описание CMOS Octal Latching Inverting Bus Driver
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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82C83H Даташит, Описание, Даташиты
82C83H
March 1997
CMOS Octal Latching Inverting Bus Driver
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld CERDIP
SMD#
20 Pad CLCC
SMD#
TEMP RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
DI0 1
DI1 2
DI2 3
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
OE 9
GND 10
20 VCC
19 DO0
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
13 DO6
12 DO7
11 STB
3 2 1 20 19
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
9 10 11 12 13
STB
X
H
H
H = Logic One
L = Logic Zero
X = Don‘t Care
TRUTH TABLE
OE DI DO
H X HI-Z
L LH
LHL
LX
HI-Z = High Impedance
= Negative Transition
= Latched to Value of Last
Data
PIN
DI0 - DI7
DO0 - DO7
STB
OE
PIN NAMES
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-281
File Number 2971.1









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82C83H Даташит, Описание, Даташиты
82C83H
Functional Diagram
DQ
DI0 CLK
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
DO0 maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
OE
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the VCC and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from VCC to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
STB
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
FIGURE 2. 82C86H/87H GATED INPUTS
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = CL (dv/dt)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
I = CL(--V-----C----C------×-----8t-R--0------t-p-F---e----r--c----e----n---t---)
(EQ. 1)
where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
I = (8 x 300 x 10-12) x (5.0V x 0.8)/(20 x 10-9) = 480mA
This current spike may cause a large negative voltage spike on
VCC which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between VCC and GND at each device,
with placement being as near to the device as possible.
ALE
MULTI-
PLEXED
BUS
ICC
ADDRESS
ADDRESS
STB
DATA IN
VCC
P
N
VCC
P
P
INTERNAL
DATA
N
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
N
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
4-282









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82C83H Даташит, Описание, Даташиты
82C83H
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Thermal Resistance (Typical)
θJAoC/W θJCoC/W
CERDIP Package . . . . . . . . . . . . . . . .
70
16
CLCC Package . . . . . . . . . . . . . . . . . .
80
20
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC
Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175oC
Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only) . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5.0V ± 10%; TA = 0oC to +70oC (C82C83H);
TA = -40oC to +85oC (I82C83H);
TA = -55oC to +125oC (M82C83H)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
VIH Logical One Input Voltage
2.0 -
2.2
V C82C83H, I82C83H,
M82C83H, (Note 1)
VIL
VOH
VOL
II
Logical Zero Input Voltage
Logical One Output Voltage
Logical Zero Output Voltage
Input Leakage Current
3.0
VCC -0.4V
-10
0.8
-
0.45
10
V
V IOH = -8mA,
IOH = -100mA, OE = GND
V IOL = 20mA, OE = GND
µA VIN = GND or VCC,
DIP Pins 1-9,11
IO Output Leakage Current
-10 10 µA VO = GND or OE VCC -0.5V
DIP Pins 12-19
lCCSB
Standby Power Supply Current
IC COP Operating Power Supply Current
-
-
10 µA VIN = VCC or GND
VCC = 5.5V Outputs Open
1 mA/ TA = +25oC, VCC = 5V, Typical
MHz
(See Note 2)
NOTES:
1. VIH is measured by applying a pulse of magnitude = VlHMIN to one data Input at a time and checking the corresponding device output for
a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at VCC -0.4V.
2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance TA = +25oC
SYMBOL
PARAMETER
CIN
COUT
Input Capacitance
Output Capacitance
TYPICAL
13
20
UNITS
pF
pF
TEST CONDITIONS
FREQ = 1MHz, all measure-
ments are referenced to device
GND
4-283










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