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NE5537D PDF даташит

Спецификация NE5537D изготовлена ​​​​«Philipss» и имеет функцию, называемую «Sample-and-hold amplifier».

Детали детали

Номер произв NE5537D
Описание Sample-and-hold amplifier
Производители Philipss
логотип Philipss логотип 

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NE5537D Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kload. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
FEATURES
Operates from ±5V to ±18V supplies
Hold leakage current 6pA @ TJ = 25°C
Less than 4µs acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01µF
Low input offset: 1MV (typical)
0.002% gain accuracy with RL=2k
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
FE and N Packages
V+ 1
OFFSET ADJUST 2
INPUT 3
V– 4
8 LOGIC
7 LOGIC REFERENCE
6 Ch
5 OUTPUT
D1 Package
INPUT 1
NC 2
V– 3
NC 4
NC 5
NC 6
OUTPUT 7
14 VOS ADJ
13 NC
12 V+
11 LOGIC
10 LOGIC REFERENCE
9 NC
8 Ch
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
3
INPUT
LOGIC 8
7
LOGIC
REFERENCE
+
+
30k
5
OUTPUT
300
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55°C to +125°C
ORDER CODE
NE5537N
NE5537D
SE5537FE
DWG #
0404B
0175D
0404B
August 31, 1994
884 853-1044 13721









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NE5537D Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VS Voltage supply
Maximum power dissipation
PD TA=25°C (still-air)1
N package
±18
1160
V
mW
D package
1090
mW
FE package
780 mW
TA
TSTG
VIN
Operating ambient temperature range
SE5537
NE5537
Storage temperature range
Input voltage
Logic to logic reference differential voltage2
-55 to +125
0 to +70
-65 to +150
Equal to supply voltage
+7, -30
°C
°C
°C
V
Output short circuit duration
Indefinite
Hold capacitor short circuit duration
10 s
TSOLD
Lead soldering temperature (10sec max)
300 °C
NOTES:
1. Derate above 25°C at the following rates:
FE package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply
voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below
the positive supply and 3V above the negative supply.
August 31, 1994
885









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NE5537D Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
Sample-and-hold amplifier
Product specification
NE/SE5537
DC ELECTRICAL CHARACTERISTICS1
SYMBOL
PARAMETER
TEST CONDITIONS
SE5537
NE5537
Min Typ Max Min Typ Max
UNIT
VOS Input offset voltage4
TJ=25°C
Full temperature range
13
5
27
10
mV
mV
IBIAS
Input bias current4
Input impedance
Gain error
TJ=25°C
Full temperature range
TJ=25°C
TJ=25°C
-10VVIN10V, RL=2k
-11.5VVIN11.5V,
RL=10k
Full temperature range
5 25
75
1010
0.002 0.007
10 50
1010
0.004
100
0.01
nA
nA
%
0.02 0.02 %
Feedthrough attenuation
ratio at 1kHz
TJ=25°C, CH=0.01µF
86 96
80 90
dB
Output impedance
TJ=25°C, “HOLD” mode
Full temperature range
“HOLD” Step2
ICC Supply current4
TJ=25°C, CH=0.01µF, VOUT=0
TJ=25°C
Logic and logic reference
0.5 2
4
0.5 2.0
4.5 6.5
0.5 4
6
1.0 2.5
4.5 7.5
mV
mA
input current
Leakage current into hold
capacitor4
TJ=25°C
TJ=25°C “hold” mode3
2 10
6 50
2 10
6 100
µA
pA
Acquisition time to 0.1%
Hold capacitor charging
current
VOUT=10V,
CH=1000pF
CH=0.01µF
VIN-VOUT=2V
4 4 µs
20 20 µs
5 5 mA
SVRR
Supply voltage rejection
ratio
VOUT=0V
80 110
80 110
dB
Differential logic threshold
TJ=25°C
0.8 1.4 2.4 0.8 1.4 2.4
V
NOTES:
1. Unless otherwise specified, the following conditions apply: Unit is in “sample” mode. VS=±15V, TJ=25°C, -11.5VVIN11.5V, CH=0.01µF, and
RL=2k. Logic reference voltage=0V and logic voltage=2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor
value.
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. These parameters guaranteed over a supply voltage range of ±5 to ±18V.
August 31, 1994
886










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