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PDF NJU6679 Data sheet ( Hoja de datos )
| Número de pieza | NJU6679 | |
| Descripción | 128-common x 132-segment BIT MAP LCD DRIVER | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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104-common x 132-segment
BIT MAP LCD DRIVER
NJU6678
PRELIMINARY
GENERAL DESCRIPTION
PACKAGE OUTLINE
The NJU6678 is a bit map LCD driver to display graphics or charac-
ters. It contains 21,120 bits display data RAM, microprocessor inter-
face circuits, instruction decoder, 132-segment and 104-common driv-
ers.
The bit image display data is transferred to the display data RAM by
serial or 8-bit parallel interface.
The NJU6678 displays 104 x 132 dots graphics or 8-character 6-line
by 16 x 16 dots character.
It oscillates by built-in OSC circuit without any external components.
Furthermore, the NJU6678 features Partial Display Function which
creates up to 2 blocks of active display area and optimizes duty cycle
ratio. This function sets optimum boosted voltage by the combination
with both of programmable 5-time voltage booster circuit and 201-
step electrical variable resistor. As result, it reduces the operating cur-
rent.
The operating voltage from 2.5V to 3.3V and low operating current are
useful for small size battery operating items.
NJU6678CL
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM - 21,120 bits (1.5 times over than display size)
236 LCD Drivers - 104-common and 132-segment
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface
Partial Display Function
(2 blocks of active display area and automatic duty cycle ratio selection)
Easy Vertical Scroll by the variable start line address and over size display data RAM
Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias
Common Driver Order Assignment by mask option
Version C0 to C103(Pin name)
NJU6678A Com0 to Com103
NJU6678B Com103 to Com0
Useful Instruction Set
Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set,
Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read,
All On/Off, Voltage Booster Circuits Multiple Select(Maximum 5-time), n-Line Inverse,
Read Modify Write, Power Saving, ADC Select, etc.
Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum),
Regulator, Voltage Follower x 4
Precision Electrical Variable Resistance
Low Power Consumption
Operating Voltage --- 2.5V to 3.3V
LCD Driving Voltage --- 6.0V to 17V
Package Outline --- COF / TCP / Bumped Chip
C-MOS Technology
Mar.2000
Ver.2.1
1 page  
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Terminal
S 102
S 103
S 104
S 105
S 106
S 107
S 108
S 109
S 110
S 111
S 112
S 113
S 114
S 115
S 116
S 117
S 118
S 119
S 120
S 121
S 122
S 123
S 124
S 125
S 126
S 127
S 128
S 129
S 130
S 131
C 103
C 102
C 101
C 100
C 99
C 98
C 97
C 96
C 95
C 94
C 93
C 92
C 91
C 90
C 89
C 88
C 87
C 86
C 85
C 84
X= um
-2190
-2250
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
Y= um
2497
2497
2370
2310
2250
2190
2130
2070
2010
1950
1890
1830
1770
1710
1650
1590
1530
1470
1410
1350
1290
1230
1170
1110
1050
990
930
870
810
750
690
630
570
510
450
390
330
270
210
150
90
30
-30
-90
-150
-210
-270
-330
-390
-450
NJU6678
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
Terminal
C 83
C 82
C 81
C 80
C 79
C 78
C 77
C 76
C 75
C 74
C 73
C 72
C 71
C 70
C 69
C 68
C 67
C 66
C 65
C 64
C 63
C 62
C 61
C 60
C 59
C 58
C 57
C 56
C 55
C 54
C 53
C 52
X= um
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
-2524
Y= um
-510
-570
-630
-690
-750
-810
-870
-930
-990
-1050
-1110
-1170
-1230
-1290
-1350
-1410
-1470
-1530
-1590
-1650
-1710
-1770
-1830
-1890
-1950
-2010
-2070
-2130
-2190
-2250
-2310
-2370
5 Page 
NJU6678
(1-8) Reset Circuit
Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.
Initialization
1 Display Off
2 Normal Display (Non-inverse display)
3 ADC Select : Normal (ADC Instruction D0 =”0”)
4 Read Modify Write Mode Off
5 Internal Power supply (Voltage Booster) circuits Off
6 Static Drive Off
7 Driver Output Off
8 Clear the serial interface register
9 Set the address(00)H to the Column Address Counter
10 Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register
11 Set the page “0” to the Page Address Register
12 Set the EVR register to (FF)H
13 Set the All display(1/104 duty)
14 Set the Bias select(1/11 Bias)
15 Set the 5-Time Voltage Booster
16 Set the n line turn over register (0)H
The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time
with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"
level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation
goes to normal.
When the internal LCD power supply is not used, the external LCD power supply into the NJU6678 must be
turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the
oscillation circuit and the output terminal conditions (D0 to D7) are not influenced. The initialization must be
performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset
Instruction performs the initialization procedures from No.8 to No.16 as shown in above.
Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the
careful design.
(1-9) LCD Driving
(a) LCD Driving Circuits
LCD driving circuits are consisted of 236 multiplexers which operate as 132 Segment drivers and 104 Com-
mon drivers. 104 Common drivers with the shift register scan the common display signal. The combination of
the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave
form is shown in the Fig. 7.
(b) Display Data Latch Circuits
Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common
cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse
ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display
Data RAM is not changed.
(c) Line Counter and Latch signal of Latch Circuits
The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock
(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display
data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving
circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by
the MPU.
(d) Display Timing Generator
Display Timing Generator generates the timing signal for the display system by combination of the master
clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate
LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NJU6679.PDF ] | |
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