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PDF NM27C256 Data sheet ( Hoja de datos )
| Número de pieza | NM27C256 | |
| Descripción | 262 /144-Bit (32K x 8) High Performance CMOS EPROM | |
| Fabricantes | National | |
| Logotipo |  |
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December 1993
NM27C256
262 144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The NM27C256 is a 256K Electrically Programmable Read
Only Memory It is manufactured in National’s latest CMOS
split gate EPROM technology which enables it to operate at
speeds as fast as 120 ns access time over the full operating
range
The NM27C256 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software Its 120 ns access time
provides high speed operation with high-performance CPUs
The NM27C256 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment
Frequently-used software routines are quickly executed
from EPROM storage greatly enhancing system utility
The NM27C256 is configured in the standard EPROM pin-
out which provides an easy upgrade path for systems which
are currently using standard EPROMs
The NM27C256 is one member of a high density EPROM
Family which range in densities up to 4 Mb
Features
Y High performance CMOS
120 ns access time
Y JEDEC standard pin configuration
28-pin DIP package
32-pin chip carrier
Y Drop-in replacement for 27C256 or 27256
Y Manufacturer’s identification code
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
HPCTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL D 10833
TL D 10833 – 1
RRD-B30M65 Printed in U S A
1 page  
Programming Characteristics (Notes 1 2 3 4 and 5)
Symbol
Parameter
Conditions
Min
Typ
Max Units
tAS
tOES
tVPS
tVCS
tDS
tAH
tDH
tDF
Address Setup Time
OE Setup Time
VPP Setup Time
VCC Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output
Float Delay
CE e VIL
1
1
1
1
1
0
1
0
ms
ms
ms
ms
ms
ms
ms
60 ns
tPW Program Pulse Width
tOE Data Valid from OE
IPP VPP Supply Current
during Programming Pulse
CE e VIL
CE e VIL
95 100 105 ms
100 ns
30 mA
ICC
TA
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
50
20 25 30
6 0 6 25 6 5
12 5 12 75 13 0
5
0 0 0 45
24 40
08 20
08 20
mA
C
V
V
ns
V
V
V
V
Programming Waveforms (Note 3)
TL D 10833 – 5
Note 1 National’s standard product warranty applies to devices programmed to specifications described herein
Note 2 VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP The EPROM must not be inserted into or removed from a
board with voltage applied to VPP or VCC
Note 3 The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V Care must be taken when switching the VPP
supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across VPP VCC to GND to suppress
spurious voltage transients which may damage the device
Note 4 Programming and program verify are tested with the Fast Program Algorithm at typical power supply voltages and timings
Note 5 During power up the PGM pin must be brought high (t VIH) either coincident with or before power is applied to VPP
5
5 Page 
Physical Dimensions inches (millimeters)
UV Window Cavity Dual-In-Line CerDIP Package (Q)
Order Number NM27C256QXXX
NS Package Number J28AQ
28-Lead Plastic One-Time-Programmable Dual-In-Line Package
OrderNumber NM27C256NXXX
NS Package Number N28B
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NM27C256.PDF ] | |
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