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8406801VA PDF даташит

Спецификация 8406801VA изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Clock Generator Driver».

Детали детали

Номер произв 8406801VA
Описание CMOS Clock Generator Driver
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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8406801VA Даташит, Описание, Даташиты
82C84A
March 1997
CMOS Clock Generator Driver
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
Ordering Information
PART
NUMBER
CP82C84A
IP82C84A
CS82C84A
IS82C84A
CD82C84A
ID82C84A
MD82C84A/B
8406801VA
MR82C84A/B
84068012A
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE
PKG.
NO.
18 Ld PDIP E18.3
E18.3
20 Ld PLCC N20.35
N20.35
18 Ld CERDIP F18.3
F18.3
F18.3
SMD#
F18.3
20 Pad CLCC J20.A
SMD#
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
RDY1 4
READY 5
RDY2 6
AEN2 7
NC 8
18 X2
17 ASYNC
16 EFI
15 F/C
14 NC
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-287
File Number 2974.1









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8406801VA Даташит, Описание, Даташиты
Functional Diagram
82C84A
RES
X1
X2
11
17
16
13
F/C
EF1
CSYNC
RDY1
AEN1
RDY2
AEN2
14
1
4
3
6
7
15
ASYNC
XTAL
OSCILLATOR
÷3
SYNC
CK
DQ
FF1
D 10
Q RESET
CK
12
OSC
÷2
SYNC
2
PCLK
8
CLK
CK 5
D Q READY
FF2
CONTROL PIN
LOGICAL 1
LOGICAL 0
F/C
External Clock
Crystal Drive
RES
Normal
Reset
RDY1, RDY2
Bus Ready
Bus Not Ready
AEN1, AEN2
Address Disabled Address Enable
ASYNC
1 Stage Ready
Synchronization
2 Stage Ready
Synchronization
4-288









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8406801VA Даташит, Описание, Даташиты
82C84A
Pin Description
SYMBOL NUMBER TYPE
DESCRIPTION
AEN1,
AEN2
3, 7
I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus
Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN
signal inputs are useful in system configurations which permit the processor to access two Multi-
Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true
(LOW).
RDY1,
RDY2
4, 6
I BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a
device located on the system data bus that data has been received, or is available RDY1 is qual-
ified by AEN1 while RDY2 is qualified by AEN2.
ASYNC
15
I READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is low, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY
5
O READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY
is cleared after the guaranteed hold time to the processor has been met.
X1, X2
17, 16
I O CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3
times the desired processor clock frequency, (Note 1).
F/C 13
I FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits
the processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is gen-
erated for the EFI input, (Note 1).
EFI 14
I EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input fre-
quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de-
sired CLK output.
CLK 8
O PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di-
rectly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crys-
tal or EFI input frequency and a 1/3 duty cycle.
PCLK
2
O PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of
CLK and has a 50% duty cycle.
OSC
12
O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal.
RES
11
I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A pro-
vides a Schmitt trigger input so that an RC connection can be used to establish the power-up
reset of proper duration.
RESET
10
O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES.
CSYNC
1
I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As
to be synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal
counters are reset. When CSYNC goes LOW the internal counters are allowed to resume count-
ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator
CSYNC should be hardwired to ground.
GND
9
Ground
VCC
18
VCC: The +5V power supply pin. A 0.1µF capacitor between VCC and GND is recommended for
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open.
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Номер в каталогеОписаниеПроизводители
8406801VACMOS Clock Generator DriverIntersil Corporation
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