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87C196KR PDF даташит

Спецификация 87C196KR изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «ADVANCED 16-BIT CHMOS MICROCONTROLLER».

Детали детали

Номер произв 87C196KR
Описание ADVANCED 16-BIT CHMOS MICROCONTROLLER
Производители Intel Corporation
логотип Intel Corporation логотип 

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87C196KR Даташит, Описание, Даташиты
87C196KR KQ 87C196JV JT 87C196JR JQ
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y b40 C to a125 C Ambient
Y High Performance CHMOS 16-Bit CPU
Y Up to 48 Kbytes of On-Chip EPROM
Y Up to 1 5 Kbytes of On-Chip Register
RAM
Y Up to 512 Bytes of Additional RAM
(Code RAM)
Y Register-Register Architecture
Y Up to 8 Channel 10-Bit A D with
Sample Hold
Y Up to 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y High Speed Peripheral Transaction
Server (PTS)
Y Two 16-Bit Software Timers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
Y Programmable Bus (HLD HLDA)
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y 68-Pin and 52-Pin PLCC Packages
Device Pins Package EPROM Reg RAM Code RAM I O EPA SIO SSIO A D
87C196KR 68-pin PLCC
16K
488
256 56 10 Y Y 8
87C196KQ 68-pin PLCC
12K
360
128 56 10 Y Y 8
87C196JV 52-pin PLCC 48K 1 5K
512
41 6
Y
Y
6
87C196JT 52-pin PLCC 32K 1 0K
512
41 6
Y
Y
6
87C196JR 52-pin PLCC
16K
488
256
41 6
Y
Y
6
87C196JQ 52-pin PLCC
12K
360
128
41 6
Y
Y
6
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller prod-
ucts implemented on Intel’s advanced 1 micron process technology These products are based on the
80C196KB device with improvements for automotive applications The instruction set is a true super set of
80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory
scalars of the 87C196KR JR
The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family
These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and
electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512
bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes
of Code RAM
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 270827-006









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87C196KR Даташит, Описание, Даташиты
87C196KR KQ 87C196JV JT 87C196JR JQ
The MCS 96 microcontroller family members are all
high performance microcontrollers with a 16-bit
CPU The 87C196Kx Jx family members listed
above are composed of the high-speed (16 MHz)
core as well as the following peripherals up to 48
Kbytes of Programmable EPROM up to 1 5 Kbytes
of Register RAM 512 bytes of code RAM (16-bit
addressing modes) with the ability to execute from
this RAM space an eight channel-10-Bit g3 LSB
analog to digital converter with programmable S H
times with conversion times k5 ms at 16 MHz an
asynchronous synchronous serial I O port (8096
compatible) with a dedicated 16-bit baud rate gener-
ator an additional synchronous serial I O port (8096
compatible) with a dedicated 16-bit baud rate gener-
ator an additional synchronous serial I O port with
full duplex master slave transceivers a flexible tim-
er counter structure with prescaler cascading and
quadrature capabilities 10 modularized multiplexed
high speed I O for capture and compare (called
Event Processor Array) with 250 ns resolution and
double buffered inputs a sophisticated prioritized in-
terrupt structure with programmable Peripheral
Transaction Server (PTS) The PTS has several
channel modes including single burst block trans-
fers from any memory location to any memory loca-
tion a PWM and PWM toggle mode to be used in
conjunction with the EPA and an A D scan mode
Additional SFR space is allocated for the EPA and
can be ‘‘windowed’’ into the lower Register RAM
area
Please refer to the following datasheets for higher
frequency versions of devices contained within this
datasheet 20 MHz 87C196JT Order 272529
20 MHz 87C196JV Order Number 272580
ARCHITECTURE
The 87C196KR KQ JV JT JR JQ are members of
the MCS 96 microcontroller family has the same ar-
chitecture and uses the same instruction set as the
80C196KB KC Many new features have been add-
ed including
CPU FEATURES
 Powerdown and Idle Modes
 16 MHz Operating Frequency
 A High Performance Peripheral Transaction Serv-
er (PTS)
 Up to 37 Interrupt Vectors
 Up to 512 Bytes of Code RAM
 Up to 1 5 Kbytes of Register RAM
 ‘‘Windowing’’ Allows 8-Bit Addressing to Some
16-Bit Addresses
 1 75 ms 16 x 16 Multiply
 3 ms 32 16 Divide
 Oscillator Fail Detect
PERIPHERAL FEATURES
 Programmable A D Conversion and S H Times
 10 Capture Compare I O with 2 Flexible Timers
 Synchronous Serial I O Port for Full Duplex Seri-
al I O
 Total Utilization of ALL Available Pins (I O Mux’d
with Control)
 2 16-Bit Timers with Prescale Cascading and
Quadrature Counting Capabilities
 Up to 12 Externally Triggered Interrupts
NEW INSTRUCTIONS
XCH XCHB
Exchange the contents of two locations either Word
or Byte is supported
BMOVi
Interruptable Block Move Instruction allows the user
to be interrupted during long executing Block Moves
TIJMP
Table Indirect JUMP This instruction incorporates a
way to do complex CASE level branches through
one instruction An example of such code savings
several interrupt sources and only one interrupt vec-
tor The TIJMP instruction will sort through the
sources and branch to the appropriate sub-code lev-
el in one instruction This instruction was added es-
pecially for the EPA structure but has other code
saving advantages
EPTS DPTS
Enable and Disable PTS Interrupts (Works like EI
and DI)
2









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87C196KR Даташит, Описание, Даташиты
87C196KR KQ 87C196JV JT 87C196JR JQ
SFR OPERATION
An additional 256 bytes of SFR registers were add-
ed to the 8XC196KR devices These locations were
added to support the wide range of on-chip peripher-
als that the 8XC196KR has This memory space
(1F00 – 1FFFH) has the ability to be addressed as
direct 8-bit addresses through the ‘‘windowing’’
technique Any 32- 64- or 128-byte section can be
relocated in the upper 32 64 or 128 bytes of the
internal register RAM (080 – FFH) address space
Figure 1 Block Diagram
270827 – 1
Figure 2 The 8XC196KR Family Nomenclature
270827 – 15
3










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Номер в каталогеОписаниеПроизводители
87C196KBCOMMERCIAL/EXPRESS CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KC16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KC16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KCCommercial / Express CHMOS MicrocontrollerIntel
Intel

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