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PDF 87C54-20 Data sheet ( Hoja de datos )
| Número de pieza | 87C54-20 | |
| Descripción | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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87C54 87C54-20
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 16 KBYTES USER PROGRAMMABLE EPROM
Automotive
Y Extended Automotive Temperature
Range (b40 C to a125 C Ambient)
Y High Performance CHMOS EPROM
Y Three 16-Bit Timer Counters
Y One-to-Three Level Program Data Lock
System
Y 16K On-Chip EPROM ROM
Y 256 Bytes of On-Chip Data RAM
Y Quick Pulse Programming Algorithm
Y Boolean Processor
Y 32 Programmable I O Lines
Y 7 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS -51 Compatible Instruction Set
Y Power Saving Idle and Power Down
Modes
Y ONCE (On-Circuit Emulation) Mode
Y RFI Reduction Mode
Y Available in 12 MHz 16 MHz and
20 MHz Versions
Y Available in PLCC and DIP Packages
(See Packaging Spec Order 231369)
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 16 Kbytes of the program memory can reside in the on-chip EPROM The device
can also address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel 87C54 is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS EPROM technology Being a member of the MCS-51 family the 87C54 uses the same powerful
instruction set has the same architecture and is pin-for-pin compatible with the existing MCS-51 family of
products The 87C54 is an enhanced version of the 87C51FB Its added features of 16 Kbytes of program
memory make it an even more powerful microcontroller for applications that require High Speed I O and
up down counting capabilities such as brake and traction control
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
February 1994
Order Number 270849-004
1 page  
AUTOMOTIVE 87C54 87C54-20
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX DPTR) In this application it
uses strong internal pullups when emitting 1’s Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX Ri) Port 2 emits the contents of
the P2 Special Function Register
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion
Port 3 Port 3 is an 8-bit bidirectional I O port with
internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally pulled low will source current
(IIL on the data sheet) because of the pullups
Port 3 also serves the functions of various special
features of the MCS-51 Family as listed below
Port Pin
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
In addition some Port 3 pins receive the high-order
address bits and act as control signals during
EPROM programming and programming verification
RST Reset input A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a minimum VIH1 is applied whether the
oscillator is running or not An internal pulldown re-
sistor permits a power-on reset with only a capacitor
connected to VCC
ALE Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory This pin (ALE PROG) is also the
program pulse input during EPROM programming for
the 87C54
In normal operation ALE is emitted at a constant
rate of the oscillator frequency and may be used
for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory
Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin
PSEN Program Store Enable is the read strobe to
external Program Memory
When the 87C54 is executing code from external
Program Memory PSEN is activated twice each
machine cycle except that two PSEN activations
are skipped during each access to external Data
Memory
EA VPP External Access enable EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH Note however that if any of the
Lock bits are programmed EA will be internally
latched on reset
EA should be strapped to VCC for internal program
executions
This pin also receives the programming supply volt-
age (VPP) during EPROM programming
XTAL1 Input to the inverting oscillator amplifier
XTAL2 Output from the inverting oscillator amplifier
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of a inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ‘‘Oscillators for Microcontrol-
lers ’’
5
5 Page 
AUTOMOTIVE 87C54 87C54-20
EXTERNAL MEMORY CHARACTERISTICS (Continued)
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
87C54 87C54-20
Min Max Min Max
TRLRH
TWLWH
TRLDV
TRHDX
RD Pulse Width
WR Pulse Width
RD Low to Valid
Data In
Data Hold After RD
High
400
400
0
6 TCLCL b 100
6 TCLCL b 100
252 5 TCLCL b 165
5 TCLCL 95
0
TRHDZ Data Float After RD
High
107
2 TCLCL b 60
TLLDV
TAVDV
TLLWL
ALE Low to Valid
Data In
Address Valid to
Valid Data In
ALE Low to RD or
WR Low
200
517 8 TCLCL b 150
8 TCLCL b 90
585 9 TCLCL b 165
9 TCLCL b 90
300 3 TCLCL b 50 3 TCLCL a 50
TAVWL
TQVWX
TWHQX
TQVWH
TRLAZ
Address Valid to
WR Low
Data Valid before
WR Low
Data Hold after WR
High
Data Valid to WR
High
RD Low to Address
Float
203
33
33
433
4 TCLCL b 130
4 TCLCL b 90
TCLCL b 50
TCLCL b 35
TCLCL b 50
TCLCL b 40
7 TCLCL b 150
7 TCLCL b 70
0
0
TWHLH RD or WR High to
ALE High
43
123
TCLCL b 40
TCLCL a 40
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
Timings speicified for the 87C54-20 are valid at 20 MHz only For timings below 20 MHz use the 87C54 timings
11
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