87C575 Datasheet PDF - NXP Semiconductors
| Part Number | 87C575 | |
| Description | 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless/ 4 comparator/ failure detect circuitry/ watchdog timer | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
80C575/83C575/87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator,
failure detect circuitry, watchdog timer
Product specification
Supersedes data of 1998 Jan 27
IC20 Data Handbook
1998 May 01
Philips
Semiconductors
|
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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
VSS
20 22 16
I Ground: 0V reference.
VCC
40 44 38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0-0.7
P1.0-P1.7
39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code
bytes during EPROM programming and outputs code bytes during program verification.
External pull-ups are required during program verification. During reset, port 0 will be
asynchronously driven low and will remain low until written to by software. All port 0 pins
have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees
positive leakage current (see DC Electrical Characteristics: IL1).
1-8 2-9 40-44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that
1-3 pins that have 1s written to them can be used as inputs but will source current when
externally pulled low (see DC Electrical Characteristics: IIL). Port 1 receives the low-order
address byte during program memory verification and EPROM programming. During reset,
port 1 will be asynchronously driven low and will remain low until written to by software. All
port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve
alternate functions as follows:
1 2 40 I/O P1.0 T2 Timer 2 external I/O – clockout (programmable)
CMP0+ Comparator 0 positive input
2 3 41 I P1.1 T2EX Timer 2 capture input
CMP0- Comparator 0 negative input
3
4 42
I P1.2 ECI
PCA count input
4 5 43 I/O P1.3 CEX0 PCA module 0 external I/O
CMP0 Comparator 0 output
5 6 44 I/O P1.4 CEX1 PCA module 1 external I/O
CMP1 Comparator 1 output
6 7 1 I/O P1.5 CEX2 PCA module 2 external I/O
CMP2 Comparator 2 output
7 8 2 I/O P1.6 CEX3 PCA module 3 external I/O
CMP3 Comparator 3 output
8 9 3 I/O P1.7 CEX4 PCA module 4 external I/O
P2.0-P2.7
P3.0-P3.7
21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them can be used as inputs, but will source current when externally pulled low
(see DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during
accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2
receives the high-order address byte during program verification and EPROM programming.
During reset, port 2 will be asynchronously driven low and will remain low until written to by
software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open
drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC
Electrical Characteristics IL1).
10-17 11,
5,
13-19 7-13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1
that have 1s written to them can be used as inputs but will source current when externally
pulled low (see DC Electrical Characteristics: IIL). P3.1 will be a high impedance pin except
while transmitting serial data, in which case the strong pull-up will remain on continuously
when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of
two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be
asynchronously driven low and will remain low until written to by software. All port 3 pins
have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV
hysteresis. Port 3 pins serve alternate functions as follows:
1998 May 01
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 87C575 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 87C575.PDF Datasheet ] | |
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