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PDF NS32FX100VF Data sheet ( Hoja de datos )
| Número de pieza | NS32FX100VF | |
| Descripción | System Controller | |
| Fabricantes | National | |
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PRELIMINARY
July 1992
NS32FX100-15 NS32FX100-20 NS32FV100-20
NS32FV100-25 NS32FX200-20 NS32FX200-25
System Controller
General Description
The NS32FX200 NS32FV100 and NS32FX100 are highly
integrated system chips designed for a FAX system based
on National Semiconductor’s embedded processors
NS32FX161 NS32FV16 or NS32FX164 The NS32FX100 is
the common core for all three system chips The
NS32FV100 and NS32FX200 offer additional functions
Throughout this document references to the NS32FX100
also apply to both the NS32FV100 and the NS32FX200
Specific NS32FV100 or NS32FX200 features are explicitly
indicated
The NS32FX200 NS32FV100 and NS32FX100 feature an
interface to devices like stepper motors printers and scan-
ners a Sigma-Delta CODEC an elapsed-time counter a
DMA controller an interrupt controller and a UART
The NS32FX200 is optimized for high-end FAX applications
such as plain-paper FAX and multifunctional peripherals
The NS32FX100 is optimized for low-cost FAX applica-
tions The NS32FV100 is optimized for thermal paper FAX
machines with Digital Answering Machine support
Features
Y Direct interface to the NS32FX161 NS32FV16 and
NS32FX164 embedded processors
Y Supports a variety of Contact Image Sensor (CIS) and
Charge Coupled Device (CCD) scanners
Y Direct interface to a variety of Thermal Print Head
(TPH) printers Bitmap shifter and DMA channels facili-
tate the connection of other types of printers
Y Supports two stepper motors
Y Direct interface to ROM and SRAM The NS32FX200
and NS32FV100 in addition interface to DRAM
devices
Y Programmable wait state generator
Y Demultiplexed address and data buses
Y Multiplexed DRAM address bus (NS32FX200 and
NS32FV100)
Y Supports 3V freeze mode by maintaining only elapsed
time counter
Y Control of power consumption by disabling inactive
modules and reducing the clock frequency
Y Operating frequency
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FX200)
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FV100)
Normal mode 14 7456 MHz 19 6608 MHz in steps
of 1 2288 MHz (NS32FX100)
Power Save mode Normal mode frequency divided
by sixteen
Y On-Chip full duplex Sigma-Delta CODEC with
Total harmonic distortion better than b70 dB
Programmable hybrid balance filter
Programmable reception and transmission filters
Programmable gain control
Y On-Chip Interrupt Control Unit with
16 interrupt sources
Programmable triggering mode
Y On-Chip counters WATCHDOGTM UART
MICROWIRETM System Clock Generator and I O
ports
Y On-Chip DMA controller (NS32FX200 four channels
NS32FX100 NS32FV100 three channels)
Y Up to 37 on-chip general purpose I O pins expandable
externally
Y Flexible allocation of I O and modules’ pins
Y 132-pin JEDEC PQFP package
FIGURE 1-1 A FAX Controller Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL EE11331
TL EE 11331 – 1
RRD-B30M105 Printed in U S A
1 page  
List of Figures (Continued)
FIGURE 4-1
FIGURE 4-2
FIGURE 4-3
FIGURE 4-4
FIGURE 4-5
FIGURE 4-6
FIGURE 4-7
FIGURE 4-8
FIGURE 4-9
FIGURE 4-10
FIGURE 4-11
FIGURE 4-12
FIGURE 4-13
FIGURE 4-14
FIGURE 4-15
FIGURE 4-16
FIGURE 4-17
FIGURE 4-18
FIGURE 4-19
FIGURE 4-20
FIGURE 4-21
FIGURE 4-22
FIGURE 4-23
FIGURE 4-24
FIGURE 4-25
FIGURE 4-26
FIGURE 4-27
Connection Diagram Top View
Analog Circuitry Block Diagram
TTL Output Signals Specification Standard
TTL Input Signals Specification Standard
CMOS Output Signals Specification Standard
CMOS Input Signals Specification Standard
Input Hysteresis
Clock Waveforms
DRAM Read Bus Cycle
DRAM Write Bus Cycle
ROM SRAM Read Bus Cycle
ROM SRAM Write Bus Cycle (One Wait State)
I O Read Bus Cycle
I O Write Bus Cycle
DRAM Refresh Bus Cycles
DMA Read Transaction (DIR e 0)
DMA Write Transaction (DIR e 1)
Interrupt Signals Timing
Sigma-Delta Signals Timing
SBYPS Input Signal Timing
Printer Signals Timing
Reset Signals Timing
Scanner Signals Timing
UART Signals Timing
MWIRE Signals Timing
Ports Signals Timing
Analog Signals Timing
List of Tables
TABLE 2-1
TABLE 2-2
TABLE 2-3
TABLE 2-4
TABLE 2-5
TABLE 3-1
TABLE 3-2
TABLE A-1
TABLE A-2
CTTL MCLON and MCLOFF Values
Component Values
Interrupt Sources and Priority Levels
DRAM Address Multiplexing
DRAM Address Sizes
R C and L Values
System Chip Operation Modes and Power Consumption
Transmitter Performance
Receiver Performance
66
69
70
70
70
70
70
79
79
80
81
82
83
83
84
85
86
87
87
87
88
88
89
90
90
91
91
12
15
40
46
46
53
53
92
93
5
5 Page 
2 0 Architecture (Continued)
2 2 2 1 External Clocks
The TCU contains two oscillators the high-speed oscillator
and the low-speed oscillator The high-speed oscillator is
the FAX system clocking source It generates the CPU clock
and after division clocks for the Sigma-Delta CODEC
scanner printer and serial communications channels A
high-speed clock signal is input to the NS32FX100 from an
external crystal through the FOSCI pin The NS32FX100
uses this signal to generate the CCLK clock which serves
as the input clock to the CPU The CPU then divides CCLK
by two and generates CTTL which serves as the bus clock
The NS32FX100 includes a PLL to ensure synchronization
between the NS32FX100 clocks and the CPU CTTL is used
to close the PLL loop and enable tracking of the CPU inter-
nal clocks
The low-speed oscillator which gets its input through the
SOSCI pin is used to keep track of elapsed time and to
operate the refresh requester This oscillator operates in
Normal mode as well as in Power Save and Freeze modes
The NS32FX100 controls the CPU running frequency It
may reduce the frequency by dividing CCLK by 16 To en-
sure accurate tracking of the CTTL phase by the
NS32FX100 clock division should be carried out via the
NS32FX100 and the power save mode of the CPU should
not be used
The slow oscillator which operates during Normal Power
Save and Freeze modes can be a 32 768 kHz oscillator for
systems with memory refresh rate of up to 8 kHz Systems
with memory refresh rate higher than 8 kHz should use a
slow oscillator of 455 kHz
2 2 2 2 Internal Clocks
The TCU module generates a 1 2288 MHz Master Clock
(MCLK) MCLK is generated by a programmable divider
which divides the CTTL input clock The MCLK clock is used
for synchronization throughout the NSFX100-based FAX
system In particular the following are derived from MCLK
CLK128 A 12 8 kHz clock
Time-Slots generator (TSL) An 8-bit down counter fed
by CLK128
The Time-Slots generator performs two functions
Division of each 20 ms period into 256 time slots
Generation of a 100 Hz System Tick (STIC)
The time slots are used to synchronize the various compo-
nents of the FAX system e g the printer and scanner with
their respective motors
The System Tick is used by both the Interrupt Control Unit
(ICU) for generating an interrupt and by the WATCHDOG
counter as described in Section 2 2 3
Several registers are provided to control and use the TCU
and I O signals These registers are described in Section
223
Note 1 When CSCL e 1 CLK128 is generated by dividing MCLK by 6
Note 2 When CSCL e 0 CLK128 is generated by dividing MCLK by 96
(MCLK is 1 2288 MHz refer to Table I for MCLON and MCLOFF values)
Note 3 CLK128 is always 12 800 Hz and STIC is always 100 Hz
FIGURE 2-2 High Speed Oscillator Clocks
TL EE 11331 – 7
FIGURE 2-3 Low Speed Oscillator Clocks
11
TL EE 11331 – 8
11 Page | ||
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