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NSBMC096-16 PDF даташит

Спецификация NSBMC096-16 изготовлена ​​​​«National» и имеет функцию, называемую «NSBMC096-16/-25/-33 Burst Memory Controller».

Детали детали

Номер произв NSBMC096-16
Описание NSBMC096-16/-25/-33 Burst Memory Controller
Производители National
логотип National логотип 

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NSBMC096-16 Даташит, Описание, Даташиты
August 1993
NSBMC096-16 -25 -33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
circuit which implements all aspects of DRAM control for
high performance systems using an i960 CA CF
SuperScalar Embedded Processor The NSBMC096 is func-
tionally equivalent to the V96BMCTM
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized
Static RAM offers a simple solution for high speed memory
systems However high cost and low density make this an
expensive and space consumptive choice
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost Their drawbacks are slower access time
and more complex control circuitry required to operate
them
The access time problem is solved if DRAMs are used in
page mode In this mode access times rival that of static
RAM The control circuit problem is resolved by the
NSBMC096
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA CF to the
page mode access protocol supported by dynamic RAMs
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access data can be
read or written at the rate of one word per system clock
cycle
Block Diagram
The NSBMC096 has been designed to allow maximum flexi-
bility in its application The full range of processor speeds is
supported for a wide range of DRAM speeds sizes and or-
ganizations
No glue logic is required because the bus interface is cus-
tomized to the i960 CA CF System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1 3 square inches It reduces design complexi-
ty space requirements and is fully derated for loading tem-
perature and voltage
Features
Y Interfaces directly to the i960 CA
Y Integrated Page Cache Management
Y Manages Page Mode Dynamic Memory devices
Y On-chip Memory Address Multiplexer Drivers
Y Supports DRAMs trom 256 kB to 64 MB
Y Bit counter timer
Y Non-interleaved or two way interleaved operation
Y 5-Bit Bus Watch Timer
Y Software-configured operational parameters
Y High-Speed Low Power CMOS technology
TL V 11805 – 1
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSBMC096TM and WATCHDOGTM are trademarks of National Semiconductor Corporation
i960 is a registered trademark of Intel Corporation
V96BMCTM is a trademark of V3 Corporation
C1995 National Semiconductor Corporation TL V 11805
RRD-B30M115 Printed in U S A









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NSBMC096-16 Даташит, Описание, Даташиты
Logic and Connection Diagrams
TL V 11805 – 2
Order Number NSBMC096VF
See Package Number VF132A
2
TL V 11805 – 3









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NSBMC096-16 Даташит, Описание, Даташиты
Pin Descriptions
TABLE I
Pin Signal Name
Pin Signal Name
Pin Signal Name
1 A14
2 A15
3 A16
4 VCC
5 A17
6 A19
44 LEB
45 TXA
46 TXB
47 VCC
48 VSS
53 AA0
91 VCC
92 VSS
93 AB4
94 AB5
95 AB6
96 AB7
7 A20
8 A18
9 A21
10 A24
11 A22
12 A23
54 AA1
55 AA2
56 AA3
57 VCC
58 VSS
59 AA4
97 VCC
98 VSS
99 AB8
100 AB9
101 AB10
102 AB11
13 A26
14 A25
15 A27
19 A31
20 A28
21 A29
60 AA5
61 AA6
62 AA7
63 VCC
64 VSS
65 AA8
103 VCC
104 VSS
105 CASB0
106 CASB1
107 CASB2
108 CASB3
22 A30
23 D C
24 SUP
25 PCLK
26 INT
27 BERR
66 AA9
67 AA10
68 AA11
69 VCC
70 VSS
71 CASA0
109 VCC
110 VSS
111 RASB0
112 RASB1
113 RASB2
114 RASB3
28 W R
29 BE0
30 DEN
31 BLAST
32 BE1
33 VSS
34 ADS
35 BE2
36 BE3
37 BTERM
38 READY
39 ID0
40 ID1
41 ID2
42 REFRESH
43 LEA
72 CASA1
73 CASA2
74 CASA3
75 VCC
76 VSS
77 RASA0
78 RASA1
79 RASA2
80 RASA3
81 VCC
82 MWEA
86 VSS
87 AB0
88 AB1
89 AB2
90 AB3
115 VCC
118 MWEB
119 VSS
120 RESET
121 A2
122 A3
123 A4
124 A5
125 A6
126 A7
127 A8
128 A9
129 A10
130 A11
131 A12
132 A13
Note In order for the switching characteristics of this device to be guaranteed it is necessary to connect all of the power pins (VCC VSS) to the appropriate power
levels The use of low impedance wiring to the power pins is required In systems using the i960 CA with its attendant high switching rates multi-layer printed circuit
boards with buried power and ground planes are required
3










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Номер в каталогеОписаниеПроизводители
NSBMC096-16NSBMC096-16/-25/-33 Burst Memory ControllerNational
National

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