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PDF NSBMC096VF Data sheet ( Hoja de datos )
| Número de pieza | NSBMC096VF | |
| Descripción | NSBMC096-16/-25/-33 Burst Memory Controller | |
| Fabricantes | National | |
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August 1993
NSBMC096-16 -25 -33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
circuit which implements all aspects of DRAM control for
high performance systems using an i960 CA CF
SuperScalar Embedded Processor The NSBMC096 is func-
tionally equivalent to the V96BMCTM
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized
Static RAM offers a simple solution for high speed memory
systems However high cost and low density make this an
expensive and space consumptive choice
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost Their drawbacks are slower access time
and more complex control circuitry required to operate
them
The access time problem is solved if DRAMs are used in
page mode In this mode access times rival that of static
RAM The control circuit problem is resolved by the
NSBMC096
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA CF to the
page mode access protocol supported by dynamic RAMs
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access data can be
read or written at the rate of one word per system clock
cycle
Block Diagram
The NSBMC096 has been designed to allow maximum flexi-
bility in its application The full range of processor speeds is
supported for a wide range of DRAM speeds sizes and or-
ganizations
No glue logic is required because the bus interface is cus-
tomized to the i960 CA CF System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1 3 square inches It reduces design complexi-
ty space requirements and is fully derated for loading tem-
perature and voltage
Features
Y Interfaces directly to the i960 CA
Y Integrated Page Cache Management
Y Manages Page Mode Dynamic Memory devices
Y On-chip Memory Address Multiplexer Drivers
Y Supports DRAMs trom 256 kB to 64 MB
Y Bit counter timer
Y Non-interleaved or two way interleaved operation
Y 5-Bit Bus Watch Timer
Y Software-configured operational parameters
Y High-Speed Low Power CMOS technology
TL V 11805 – 1
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSBMC096TM and WATCHDOGTM are trademarks of National Semiconductor Corporation
i960 is a registered trademark of Intel Corporation
V96BMCTM is a trademark of V3 Corporation
C1995 National Semiconductor Corporation TL V 11805
RRD-B30M115 Printed in U S A
1 page  
Pin Descriptions (Continued)
MEMORY INTERFACE
The NSBMC960 is designed to drive a memory array orga-
nized as 2 leaves each of 32 bits The address and control
signals for the memory array are output through high current
drivers in order to minimize propagation delay due to input
impedance and trace capacitance External array drivers
are not required The address and control signals however
should be externally terminated
Pin
A(A B)0 – 11
RAS(A B)0–3
CAS(A B)0–3
MWE(A B)
REFRESH
Description
Multiplexed Address Bus (Output 24 mA) These two buses transfer the multiplexed row and column
addresses to the memory array leaves A and B When non-interleaved operation is selected only address bus A
should be used
Row Address Strobes (Output 12 mA Active Low) These strobes indicate the presence of a valid row
address on busses A(A B)0–11 These signals are to be connected one to each leaf of memory Four banks of
interleaved memory may be attached to a NSBMC960
Column Address Strobe (Output 12 mA Active Low) These strobes latch a column address from A(A B)0 –
11 They are assigned one to each byte in a leaf
Memory Write Enable (Output 24 mA Active Low) These are the DRAM write strobes One is supplied for
each leaf to minimize signal loading
Refresh in progress (Output 12 mA Active Low) This output gives notice that a refresh cycle is to be
executed The timing leads refresh RAS by one cycle
BUFFER CONTROLS
Buffer control signals are provided to simplify the control of
the interface between the DRAM and i960 data busses
Multiple operating modes facilitate choice of buffer type
and simple bus buffers (‘‘245’’s) bus latches (‘‘543’’s) and
bus registers (‘‘646’’s) are all supported
Pin
TX(A B)
LE(A B)
Description
Data Bus Transmit A and B (Output Active Low) These outputs are multi-function signals The signal names
as they appear on the logic symbol are the default signal names (Mode e 0) The purpose of these outputs is to
control buffer output enables during data read transactions and in effect control the multiplexing of data from
each memory leaf onto the i960 CA CF data bus
Data Bus Latch Enable A and B (Output Active Low) These outputs are mode independent however the
timing of the signals change for different operational modes They control transparent latches that hold data
transmiffed during a write transaction In modes 0 and 1 the latch controls follow the timing of CAS for each
leaf while in modes 2 and 3 the timing of LEA and LEB is shortened to clock
5
5 Page 
Timing Parameters
INTERFACE TIMING
The NSBMC096 interface to the i960 CA CF has been de-
signed for direct interconnect It is not necessary to place
other Iogic devices between the processor and the
NSBMC096 nor is their use encouraged The introduction
of intermediate address or control signal buffers can result
in skews or delays that will require the system clock fre-
quency to be derated for operation under worst case condi-
tions The timing diagrams presented in this section assume
that all signals between the processor and the NSBMC096
are un-buffered
REFRESH TIMING
Figure 5 details the timing of the RAS only refresh per-
formed by the memory controller when there is a competing
request from a bus master A competing request is defined
as any request that occurs between T0 and T5 For any
request in this range the timing is exactly as shown As
illustrated the diagram represents the timing that results
when Cycle Extend is disabled If Cycle Extend is enabled
an additional cycle is inserted at T3 and T8
SIMPLE ACCESS TIMING
The NSBMC096 can return data to the processor in only 3
or 4 clock cycles for a basic access (2 or 3 wait states)
depending on whether Cycle Extend is enabled If multiple
access cycles are requested back to back then the BMC will
pause for a minimum of 2 clocks between RAS cycles to
insure that the RAS pre-charge time is met This will result in
5 or 6 clocks between successive simple cycles
Figure 6 shows the timing relationship between the system
clock processor control signals and NSBMC096 outputs
AIl NSBMC096 outputs are derived synchronously with the
exception of tARA (processor address to row address de-
lay) Two simple access cycles are shown in the diagram
The first is a read cycle that assumes that the NSBMC096
was idle prior to the start of the cycle the second is backed
onto the first to show the effect of RAS pre-charge imposed
by NSBMC096 If Cycle Extend is enabled a wait state will
be inserted after cycles T3 and T8
BURST ACCESS TIMING
When a burst access is requested by the processor the
NSBMC096 generates the sequence in Figure 7 If the burst
is for 2 words (load double for example) the processor gen-
erates BLAST in T5 and the sequence is shortened appro-
priately The first access of the burst sequence begins in the
same manner as a simple access Consequently the timing
parameters from Figure 6 may be applied in Figure 7
FIGURE 5 Refresh Timing
TL V 11805 – 8
11
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