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PDF NSC800 Data sheet ( Hoja de datos )
| Número de pieza | NSC800 | |
| Descripción | NSC800TM High-Performance Low-Power CMOS Microprocessor | |
| Fabricantes | National | |
| Logotipo |  |
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June 1992
NSC800TM High-Performance
Low-Power CMOS Microprocessor
General Description
The NSC800 is an 8-bit CMOS microprocessor that func-
tions as the central processing unit (CPU) in National Semi-
conductor’s NSC800 microcomputer family National’s
microCMOS technology used to fabricate this device pro-
vides system designers with performance equivalent to
comparable NMOS products but with the low power advan-
tage of CMOS Some of the many system functions incorpo-
rated on the device are vectored priority interrupts refresh
control power-save feature and interrupt acknowledge The
NSC800 is available in dual-in-line and surface mounted
chip carrier packages
The system designer can choose not only from the dedicat-
ed CMOS peripherals that allow direct interfacing to the
NSC800 but from the full line of National’s CMOS products
to allow a low-power system solution The dedicated periph-
erals include NSC810A RAM I O Timer NSC858 UART
and NSC831 I O
All devices are available in commercial industrial and mili-
tary temperature ranges along with two added reliability
flows The first is an extended burn in test and the second is
the military class C screening in accordance with Method
5004 of MIL-STD-883
Features
Y Fully compatible with Z80 instruction set
Powerful set of 158 instructions
10 addressing modes
22 internal registers
Y Low power 50 mW at 5V VCC
Y Unique power-save feature
Y Multiplexed bus structure
Y Schmitt trigger input on reset
Y On-chip bus controller and clock generator
Y Variable power supply 2 4Vb6 0V
Y On-chip 8-bit dynamic RAM refresh circuitry
Y Speed 1 0 ms instruction cycle at 4 0 MHz
NSC800-4 4 0 MHz
NSC800-35 3 5 MHz
NSC800-3 2 5 MHz
NSC800-1 1 0 MHz
Y Capable of addressing 64k bytes of memory and 256
I O devices
Y Five interrupt request lines on-chip
Block Diagram
NSC800TM is a trademark of National Semiconductor Corp
TRI-STATE is a registered trademark of National Semiconductor Corp
Z80 is a registered trademark of Zilog Corp
C1995 National Semiconductor Corporation TL C 5171
TL C 5171 – 73
RRD-B30M105 Printed in U S A
1 page  
4 0 AC Electrical Characteristics VCC e 5V g10% GND e 0V unless otherwise specified (Continued)
Symbol
Parameter
NSC800-1 NSC800-3 NSC800-35 NSC800-4 Units
Min Max Min Max Min Max Min Max
Notes
TH(ADH)1 A(8 – 15) Hold Time During 0 0 0
Opcode Fetch
0 ns
TH(ADH)2 A(8 – 15) Hold Time During 400
Memory or IO RD and WR
100
85
60 ns
TH(ADL)
TH(WD)
tINH
tINS
tNMI
tRDH
tRFLF
AD(0–7) Hold Time
Write Data Hold Time
Interrupt Hold Time
Interrupt Set-Up Time
Width of NMI Input
Data Hold after Read
RFSH Rising to ALE
Falling
100
400
0
100
50
0
60
60
100
0
50
30
0
50
35
85
0
50
25
0
45
30 ns
75 ns
0 ns
45 ns
20 ns
0 ns
40 ns
tRL(MR) RD Rising to ALE Rising
(Memory Read)
390
100
50
45 ns
tS(AD)
tS(ALE)
AD(0–7) Set-Up Time
A(8–15) SO SI IO M
Set-Up Time
300
350
45
70
45
55
40 ns
50 ns
tS(WD) Write Data Set-Up Time
385
75
35
30 ns
tW(ALE) ALE Width
430 130 115 100 ns
tWH WAIT Hold Time
00 0
0 ns
tW(I) Width of INTR RSTA-C 500 200 140 125 ns
PS BREQ
tW(INTA) INTA Strobe Width
1000
400
225
200
ns Add two t states for first
INTA of each interrupt
response string Add t for
each WAIT state
tWL WR Rising to ALE Rising 450
130
70
70 ns
tW(RD) Read Strobe Width During 960 360 210 185 ns Add t for each WAIT
Opcode Fetch
State Add t 2 for Memory
Read Cycles
tW(RFSH) Refresh Strobe Width
1925
725
450
395
tWS WAIT Set-Up Time 100 70
60
55
tW(WAIT) WAIT Input Width
550 250 195
175
tW(WR) Write Strobe Width 985 370 250
220
tXCF
XIN to Clock Falling
25 100 15 95 5 90 5 80
tXCR
XIN to Clock Rising
25 85 15 85 5 90 5 80
Note 1 Test conditions t e 1000 ns for NSC800-1 400 ns for NSC800 285 ns for NSC800-35 250 ns for NSC800-4
Note 2 Output timings are measured with a purely capacitive load of 100 pF
ns
ns
ns
ns
ns
ns
Add t for each WAIT state
5
5 Page 
8 0 Functional Description (Continued)
8 1 REGISTER ARRAY
The NSC800 register array is divided into two parts the
dedicated registers and the working registers as shown in
Figure 2
V W V WMain Reg Set
Alternate Reg Set
Accumulator Flags Accumulator Flags
A FA F
B C B C Working
*D E D E Registers
H LH L
Interrupt
Vector I
Memory
Refresh R
Index Register IX
Index Register IY
Stack Pointer SP
Program Counter PC
Dedicated
Registers
–
FIGURE 2 NSC800 Register Array
8 2 DEDICATED REGISTERS
There are 6 dedicated registers in the NSC800 two 8-bit
and four 16-bit registers (see Figure 3 )
Although their contents are under program control the pro-
gram has no control over their operational functions unlike
the CPU working registers The function of each dedicated
register is described as follows
CPU Dedicated Registers
Program Counter PC
Stack Pointer SP
Index Register IX
Index Register IY
Interrupt Vector Register I
Memory Refresh Register R
(16)
(16)
(16)
(16)
(8)
(8)
FIGURE 3 Dedicated Registers
8 2 1 Program Counter (PC)
The program counter contains the 16-bit address of the cur-
rent instruction being fetched from memory The PC incre-
ments after its contents have been transferred to the ad-
dress lines When a program jump occurs the PC receives
the new address which overrides the incrementer
There are many conditional and unconditional jumps calls
and return instructions in the NSC800’s instruction reper-
toire that allow easy manipulation of this register in control-
ling the program execution (i e JP NZ nn JR Zd2 CALL
NC nn)
8 2 2 Stack Pointer (SP)
The 16-bit stack pointer contains the address of the current
top of stack that is located in external system RAM The
stack is organized in a last-in first-out (LIFO) structure The
pointer decrements before data is pushed onto the stack
and increments after data is popped from the stack
Various operations store or retrieve data on the stack This
along with the usage of subroutine calls and interrupts al-
lows simple implementation of subroutine and interrupt
nesting as well as alleviating many problems of data manip-
ulation
8 2 3 Index Register (IX and IY)
The NSC800 contains two index registers to hold indepen-
dent 16-bit base addresses used in the indexed addressing
mode In this mode an index register either IX or IY con-
tains a base address of an area in memory making it a point-
er for data tables
In all instructions employing indexed modes of operation
another byte acts as a signed two’s complement displace-
ment This addressing mode enables easy data table ma-
nipulations
8 2 4 Interrupt Register (I)
When the NSC800 provides a Mode 2 response to INTR
the action taken is an indirect call to the memory location
containing the service routine address The pointer to the
address of the service routine is formed by two bytes the
high-byte is from the I Register and the low-byte is from the
interrupting peripheral The peripheral always provides an
even address for the lower byte (LSBe0) When the proc-
essor receives the lower byte from the peripheral it concate-
nates it in the following manner
I Register
External byte
8 bits
0
u
The LSB of the external byte must be zero
FIGURE 4a Interrupt Register
The even memory location contains the low-order byte the
next consecutive location contains the high-order byte of
the pointer to the beginning address of the interrupt service
routine
8 2 5 Refresh Register (R)
For systems that use dynamic memories rather than static
RAM’s the NSC800 provides an integral 8-bit memory re-
fresh counter The contents of the register are incremented
after each opcode fetch and are sent out on the lower por-
tion of the address bus along with a refresh control signal
This provides a totally transparent refresh cycle and does
not slow down CPU operation
The program can read and write to the R register although
this is usually done only for test purposes
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NSC800.PDF ] | |
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