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NT68P61A PDF даташит

Спецификация NT68P61A изготовлена ​​​​«ETC» и имеет функцию, называемую «8-Bit Microcontroller for Monitor (24K OTP ROM Type)».

Детали детали

Номер произв NT68P61A
Описание 8-Bit Microcontroller for Monitor (24K OTP ROM Type)
Производители ETC
логотип ETC логотип 

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NT68P61A Даташит, Описание, Даташиты
NT68P61A
8-Bit Microcontroller for Monitor (24K OTP ROM Type)
Features
T 40 pin DIP & 42 pin SDIP package
T Operating Voltage Range: 4.5V to 5.5V
T CMOS technology for low power consumption
T Crystal oscillator or ceramic resonator* available
T 6502 8-bit CMOS CPU core
T 8MHz operation of frequency
T 24K bytes of OTP (one time programming) ROM
T 256 bytes of RAM (which stores EDID for DDC1/2B)
T One 8-bit pre-loadable base timer
T 14 channels of 8 bit PWM outputs:
6 channel with 5V open drain and 8 channel with 12V
open drain
T 2 channel A/D converters with 6-bit resolution
T 24 bi-directional I/O port pins and 1 I/P pin
General Description
NT68P61A is a monitor component µC for auto-sync and
digital controlled applications. It contains a 6502
8-bit CPU core, 256 bytes of RAM used as working RAM
and stack area, 24K bytes of OTP ROM**, 14-channel 8-
bit PWM D/A converters, 2-channel A/D converters for
key detection saving I/O pins, one 8 bit pre-loadable
base timer, internal Hsync and Vsync signals processor
providing mode detection, watch-dog timer preventing
system from abnormal operation, and an I2C bus
interface. The LVRC enables NT68P61A operate
properly.
T Hsync/Vsync signal processor
T Hardware sync signals polarity & freq. evaluator
T Built-In I2C bus interface
T Supporting VESA DDC1/2B function
T Six-interrupt sources
- INTV (Vsync INT)
- INTE (External INT with rising edge trigger)
- INTMR (Timer INT )
- INTA (Slave Address Matched INT)
- INTD (Shift Register INT)
- INTS (SCL GO-LOW INT)
T Hardware watch-dog timer function
T Built-In Low Voltage reset circuit (LVRC)
Users can store EDID data in the 128 bytes of RAM for
DDC1/2B, so that users can save the cost of dedicated
EEPROM for EDID. Half frequency output function can
save external one-shot circuit. All of these designs create
savings in component costs.
* The frequency deviation of ceramic resonator has
+/- 6% maximum.
** The NT6861 (MASK ROM type) will provide
4/8/12/16/24K bytes program ROM.
1 V1.0









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NT68P61A Даташит, Описание, Даташиты
Pin Configuration
[OE] DAC2
DAC1
DAC0
[VPP] RESET
VDD
GND
OSCO
OSCI
P15
[CE] P14
[A11] P13/HALFHI
[A10] P12/HALFHO
[A9] P11/AD1
[A8] P10/AD0
P16/INTE
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSYNCI/INTV/ [A14]
39 HSYNCI
38 DAC3 [PGM]
37 DAC4 [MODE0]
36 DAC5 [MODE1]
35 DAC6 [MODE2]
34 DAC7
33 P07/HSYNCO [A7]
32 P06/VSYNCO [A6]
31 P05/DAC13 [A5]
30 P04/DAC12 [A4]
29 P03/DAC11 [A3]
28 P02/DAC10 [A2]
27 P01/DAC9 [A1]
26 P00/DAC8 [A0]
25 P31/SCL [A13]
24 P30/SDA [A12]
23 P20 [DB0]
22 P21 [DB1]
21 P22 [DB2]
* [ ]: OTP Mode
Block Diagram
NT68P61A
[OE] DAC2
DAC1
DAC0
[VPP] RESET
V DD
NC
GND
OSCO
OSCI
P15
[CE] P14
[A11] P13/HALFHI
[A10] P12/HALFHO
[A9] P11/AD1
[A8] P10/AD0
P16/INTE
[DB7] P27
[DB6]P26
[DB5] P25
[DB4] P24
[DB3] P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSYNCI/INTV
41 HSYNCI
40 DAC3 [PGM]
39 DAC4 [MODE0]
38 DAC5 [MODE1]
37 NC
36 DAC6 [MODE2]
35 DAC7 [A14]
34 P07/HSYNCO [A7]
33 P06/VSYNCO [A6]
32 P05/DAC13 [A5]
31 P04/DAC12 [A4]
30 P03/DAC11 [A3]
29 P02/DAC10 [A2]
28 P01/DAC9 [A1]
27 P00/DAC8 [A0]
26 P31/SCL [A13]
25 P30/SDA [A12]
24 P20 [DB0]
23 P21 [DB1]
22 P22 [DB2]
* [ ]: OTP Mode
VDD
GND
OSCI
OSCO
INTE
VSYNCI/INTV
HSYNCI
VSYNCO
HSYNCO
HALFHI
HALFHO
Timing Generator
CPU core
6502
Interrupt
Controller
H/V Sync Signals
Processor
OTP Program ROM
24K Bytes
SRAM + STACK
256 Bytes
8 Bit Base Timer
Watch Dog Timer
IIC BUS
PWM DACs
A/D Converter
I/O Ports
LVRC
SCL
SDA
DAC0 - DAC7
DAC8 - DAC13
AD0 - AD1
P00 - P07
P10 - P15
P16
P20 - P27
P30 - P31
2









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NT68P61A Даташит, Описание, Даташиты
NT68P61A
Pin Descriptions
Pin No.
40 Pin 42 Pin
Designation Reset Init.
I/O
Description
11
DAC2
[ OE ]
O Open drain 12V, D/A converter output 2
[ I ] [OTP ROM program output enable]
22
DAC1
O Open drain 12V, D/A converter output 1
33
DAC0
O Open drain 12V, D/A converter output 0
44
RESET
[ VPP ]
I Schmitt trigger input pin, low active reset**
[ P ] [OPT ROM program supply voltage]
55
VDD
P Power
67
GND
P Ground
78
OSCO
O Crystal OSC output
89
OSCI
I Crystal OSC input
9 10
P15
I/O Bi-directional I/O pin
10 11
P14
[ CE ]
I/O Bi- directional I/O pin
[ I ] [OTP ROM program chip enable]
11
12 P13/HALFHI
P13
I/O Bi- directional I/O pin, shared with half hsync input
[ A11 ]
[ I ] [OTP ROM program address buffer]
12
13 P12/HALFHO
P12
I/O Bi- directional I/O pin, shared with half hsync output
[ A10 ]
[ I ] [OTP ROM program address buffer]
13 14
P11/AD1
[ A9 ]
P11 I/O Bi- directional I/O pin, shared with A/D converter channel
1 input
[ I ] [OTP ROM program address buffer]
14 15
P10/AD0
[ A8 ]
P10 I/O Bi- directional I/O pin, shared with A/D converter
channel 0 input
[ I ] [OTP ROM program address buffer]
15 16 P16/INTE P16 I Schmitt trigger input pin with internal pull high, shared
with external Rising-edge trigger interrupt
16 - 23 17 - 24
P27 - P20
[ DB7 ] -
[ DB0 ]
I/O Bi- directional I/O pin, push-pull structure with high current
drive/sink capability
[ I/O ] [OTP ROM program data buffer]
24 25 P30/SDA
[ A12 ]
P30 I/O Open drain 5V Bi-direction I/O pin P30, shared with SDA
pin of I2C bus schmitt trigger buffer
[ I ] [OTP ROM program address buffer]
25 26
P31/SCL
[ A13 ]
P31 I/O Open drain 5V Bi-direction I/O pin P31, shared with SCL
pin of I2C bus schmitt trigger buffer
[ I ] [OTP ROM program address buffer]
26 27 P00/DAC8
[ A0 ]
P00 I/O Bi- directional I/O pin, shared with open drain 5V D/A
converter output 8
[ I ] [OTP ROM program address buffer]
* [ ]: OTP Mode
** This RESET pin must be pulled high by external pulled-up resistor (5Ksuggestion), or it will stay low
voltage to reset system all the time.
3










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