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PDF NT68P62-01 Data sheet ( Hoja de datos )
| Número de pieza | NT68P62-01 | |
| Descripción | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) | |
| Fabricantes | ETC | |
| Logotipo |  |
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NT68P62-01
8-Bit Microcontroller for Monitor (32K OTP ROM Type)
Features
n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K bytes of OTP (one time programming) ROM
n 512 bytes of RAM
n One 8-bit base timer
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/vsync signals processor for separate &
composite signal, including hardware sync signals
polarity detection and freq. counters with 2 sets of
Hsync counting interval
n Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n Two built-in I2C bus interfaces support VESA
DDC1/2B+
n Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
n Hardware watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT68P62 is a new generation of monitor µC for auto-
sync and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channel of 8-bit
PWM D/A converters, 4-channel A/D converters for keys
detection which can save I/O pins, one 8-bit pre-loadable
base timer, internal Hsync and Vsync signals processor,
and a watch-dog timer which prevents the system from
abnormal operation and two I2C bus interface. The user
can store EDID data in the 128 bytes of RAM for DDC1/2B,
so that user can reduce a dedicated EEPROM for EDID.
And Half frequency output function can save external one-
shot circuit. All of these designs are committed to offer our
user saving component cost. The 42 pin S-DIP IC provides
two additional I/O pins – port40 & port41, Part number
NT68P62U represents the S-DIP IC. For future reference,
port40 & port42 is only available for the 42 pin S-DIP IC.
1 V2.2
1 page  
NT68P62-01
Pin Description (continued)
Pin No.
40 Pin 42 Pin
37 39
Designation
DAC4/SCL1
38 40
[ MODE1 ]
DAC3
[ MODE0 ]
39 41
HSYNCI
Reset Init.
40 42 VSYNCI/INTV VSYNCI
-6
- 37
[ A14 ]
P40
P41
I/O Description
O Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I2C bus, Schmitt Trigger buffer
[ I ] [ OTP ROM mode select ]
O Open drain 5V, D/A converter output 3
[ I ] [ OTP ROM mode select ]
I Debouncing & Schmitt Trigger input pin for video horizontal
sync signal, internal pull high, shared with composite sync
input
I Debouncing & Schmitt trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
[ I ] external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22KΩ register
[ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22KΩ register,
only 42 pin S-DIP available
I/O Bi-directional I/O pin with internal pulled up 22KΩ register,
only 42 pin S-DIP available
* This RESET pin must be pulled high by external pulled-up register (5KΩ suggestion), or it will remain in low voltage to
continually rest system.
5
5 Page 
NT68P62-01
System Registers (continued)
Addr. Register INIT Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1
Bit0 R/W
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests
$0016 NMIPOLL 00H
-
-
-
-
-
-
INTE0
INTMUTE R
- - - - - - CLRE0 CLRMUTE W
$0017 IRQPOLL 00H
-
-
-
-
-
IRQ2
IRQ1
IRQ0
R
Control Registers of Interrupt Enable
$0018
IENMI
00H
-
-
-
-
-
-
INTE0
INTMUTE RW
$0019
IEIRQ0
00H
-
-
INTS0
INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 RW
$001A
IEIRQ1
00H
-
-
INTS1
INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 RW
$001B
IEIRQ2
00H
-
-
-
-
INTADC
INTV
INTE1
INTMR RW
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
IRQ0
00H
-
-
INTS0
INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 R
- - CLRS0 CLRA0 CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0 W
$001D
IRQ1
00H
-
-
INTS1
INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 R
- - CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 W
$001E
IRQ2
00H
-
-
-
-
INTADC
INTV
INTE1
INTMR
R
-
-
-
-
CLRADC CLRV
CLRE1
CLRMR W
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts
$001F TRIGGER FFH
-
-
-
-
- INTVR INTE1R INTE0R R/W
Control Registers for Clearing Watch Dog Timer
$0020 CLR WDT
-
0
1
01
0
1
0
1W
Control Register for DDC1/2B+ of Channel 0
$0021 CH0ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
-W
$0022 CH0TXDAT 00H
TX7
TX6
TX5 TX4
TX3
TX2
TX1
TX0 W
$0023 CH0RXDAT 00H
RX7
RX6
RX5 RX4
RX3
RX2
RX1
RX0 R
$0024 CH0CON E0H ENDDC MD1/ 2
-
START
STOP
-
TXACK
-
W
-
-
SRW
START
STOP
-
-
-R
$0025
CH0CLK
FFH MODE
MRW RSTART
-
- DDC2BR2 DDC2BR1 DDC2BR0 W
Control Register for DDC1/2B+ of Channel 1
$0026 CH1ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
-W
$0027 CH1TXDAT 00H
TX7
TX6
TX5 TX4
TX3
TX2
TX1
TX0 W
$0028 CH1RXDAT 00H
RX7
RX6
RX5 RX4
RX3
RX2
RX1
RX0 R
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT68P62-01.PDF ] | |
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