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NT68P62U PDF даташит

Спецификация NT68P62U изготовлена ​​​​«ETC» и имеет функцию, называемую «8-Bit Microcontroller for Monitor (32K OTP ROM Type)».

Детали детали

Номер произв NT68P62U
Описание 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
Производители ETC
логотип ETC логотип 

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NT68P62U Даташит, Описание, Даташиты
NT68P62-01
8-Bit Microcontroller for Monitor (32K OTP ROM Type)
Features
n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K bytes of OTP (one time programming) ROM
n 512 bytes of RAM
n One 8-bit base timer
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/vsync signals processor for separate &
composite signal, including hardware sync signals
polarity detection and freq. counters with 2 sets of
Hsync counting interval
n Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n Two built-in I2C bus interfaces support VESA
DDC1/2B+
n Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
n Hardware watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT68P62 is a new generation of monitor µC for auto-
sync and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channel of 8-bit
PWM D/A converters, 4-channel A/D converters for keys
detection which can save I/O pins, one 8-bit pre-loadable
base timer, internal Hsync and Vsync signals processor,
and a watch-dog timer which prevents the system from
abnormal operation and two I2C bus interface. The user
can store EDID data in the 128 bytes of RAM for DDC1/2B,
so that user can reduce a dedicated EEPROM for EDID.
And Half frequency output function can save external one-
shot circuit. All of these designs are committed to offer our
user saving component cost. The 42 pin S-DIP IC provides
two additional I/O pins – port40 & port41, Part number
NT68P62U represents the S-DIP IC. For future reference,
port40 & port42 is only available for the 42 pin S-DIP IC.
1 V2.2









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NT68P62U Даташит, Описание, Даташиты
Pin Configurations
40-Pin P-DIP
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[VPP] RESET
VDD
GND
OSCO
OSCI
P15/INTE0
[CE] P14/PATTERN
[A11] P13/HALFI
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P16/INTE1
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSYNCI/INTV [A14]
39 HSYNCI
38 DAC3 [MODE0]
37 DAC4/SCL1 [MODE1]
36 DAC5/SDA1 [MODE2]
35 DAC6 [RESET]
34 CREG
33 P07/HSYNCO [A7]
32 P06/VSYNCO [A6]
31 P05/DAC12 [A5]
30 P04/DAC11 [A4]
29 P03/DAC10 [A3]
28 P02/DAC9 [A2]
27 P01/DAC8 [A1]
26 P00/DAC7 [A0]
25 P31/SCL0 [A13]
24 P30/SDA0 [A12]
23 P20 [DB0]
22 P21 [DB1]
21 P22 [DB2]
* [ ]: OTP Mode
NT68P62-01
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[VPP] RESET
VDD
P40
GND
OSCO
OSCI
P15/INTE0
[CE] P14/PATTERN
[A11] P13/HALFI
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P16/INTE1
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSYNCI/INTV [A14]
41 HSYNCI
40 DAC3 [MODE0]
39 DAC4/SCL1 [MODE1]
38 DAC5/SDA1 [MODE2]
37 P41
36 DAC6 [RESET]
35 CREG
34 P07/HSYNCO [A7]
33 P06/VSYNCO [A6]
32 P05/DAC12 [A5]
31 P04/DAC11 [A4]
30 P03/DAC10 [A3]
29 P02/DAC9 [A2]
28 P01/DAC8 [A1]
27 P00/DAC7 [A0]
26 P31/SCL0 [A13]
25 P30/SDA0 [A12]
24 P20 [DB0]
23 P21 [DB1]
22 P22 [DB2]
* [ ]: OTP Mode
Block Diagram
42-Pin S-DIP
VDD
CREG
GND
OSCI
OSCO
INTE0/1
VSYNCI/INTV
HSYNCI
VSYNCO
HSYNCO
PATTERN
HALFI
HALFO
Voltage
Regulator
Timing Generator
CPU core
6502
Interrupt
Controller
H/V Sync Signals
Processor
OTP Program ROM
32K Bytes
SRAM + STACK
512 Bytes
8-Bit Base Timer
Watch Dog Timer
IIC BUS
PWM DACs
A/D Converter
I/O Ports
SCL0
SDA0
SCL1
SDA1
DAC0 - DAC7
DAC8 - DAC12
ADC0 - ADC3
P00 - P07
P10 - P16
P20 - P27
P30 - P31
P40 - P41
2









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NT68P62U Даташит, Описание, Даташиты
NT68P62-01
Pin Description
Pin No.
40 Pin 42 Pin
11
22
33
44
55
67
78
89
9 10
10 11
11 12
12 13
13 14
14 15
15 16
Designation Reset Init.
DAC2
[ PGM ]
DAC1/ADC3
DAC1
DAC0/ADC2
[ OE ]
RESET
[ VPP ]
VDD
GND
OSCO
OSCI
P15/INTE0
DAC0
P14/PATTERN
[ A15/CE ]
P13/HALFI
[ A11 ]
P12/HALFO
[ A10 ]
P11/ADC1
[ A9 ]
P10/ADC0
[ A8 ]
P16/INTE1
P13
P12
P11
P10
P16
I/O Description
O Open drain 5V, D/A converter output 2
[ I ] [OTP ROM program control]
O Open drain 5V, D/A converter output 1, shared with A/D
converter channel 3 input
O Open drain 5V, D/A converter output 0, shared with A/D
converter channel 2 input
[OTP ROM program output enable]
I Schmitt Trigger input pin, low active reset with internal
pulled down 50Kregister *
[ P ] [OTP ROM program supply voltage]
P Power
P Ground
O Crystal OSC output
I Crystal OSC input
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with input pin of external interrupt source0 (NMI),
with schmitt trigger, selectable triggered, and internal pulled
up 22Kregister
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with the output of self test pattern
[ I ] [ OTP ROM program address buffer & chip enable ]
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with half hsync input, shared with A/D converter
channel 3 input
[ I ] [ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with half hsync output
[ I ] [ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with A/D converter channel 1 input
[ I ] [ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with A/D converter channel 0 input
[ I ] [ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22Kregister,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22Kregister
3










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