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PDF NTD3055L104T4G Data sheet ( Hoja de datos )
| Número de pieza | NTD3055L104T4G | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON | |
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NTD3055L104
Power MOSFET
12 Amps, 60 Volts, Logic Level
N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
• Pb−Free Packages are Available
• Lower RDS(on)
• Lower VDS(on)
• Tighter VSD Specification
• Lower Diode Reverse Recovery Time
• Lower Reverse Recovery Stored Charge
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage, Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGS
60
60
"15
"20
Vdc
Vdc
Vdc
ID
ID
IDM
PD
TJ, Tstg
12
10
45
48
0.32
2.1
1.5
−55 to
+175
Adc
Apk
W
W/°C
W
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH
IL(pk) = 11 A, VDS = 60 Vdc)
Thermal Resistance, − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS 61 mJ
RqJC
RqJA
RqJA
TL
3.13 °C/W
71.4
100
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
http://onsemi.com
V(BR)DSS
60 V
RDS(on) TYP
104 mW
ID MAX
12 A
N−Channel
D
G
S
MARKING
DIAGRAMS
12
3
4
DPAK
CASE 369C
STYLE 2
4
Drain
1
Gate
2
Drain
3
Source
4
DPAK−3
CASE 369D
STYLE 2
4
Drain
1
2
3
12 3
Gate Drain Source
55L104
A
Y
W
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 4
1
Publication Order Number:
NTD3055L104/D
1 page  
NTD3055L104
6
5
Q1
4
QT
Q2
1000
100
tr
3
VGS
2
1
ID = 12 A
TJ = 25°C
0
02 4 6
QG, TOTAL GATE CHARGE (nC)
8
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
tf
10
1
1
td(off)
td(on)
VDS = 30 V
ID = 12 A
VGS = 5 V
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
VGS = 0 V
14
12
10
TJ = 150°C
8
TJ = 25°C
6
4
2
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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