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PDF 93C06 Data sheet ( Hoja de datos )
| Número de pieza | 93C06 | |
| Descripción | 256 Bit/1K 5.0V CMOS Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 93C06 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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93C06/46
256 Bit/1K 5.0V CMOS Serial EEPROM
FEATURES
• Low power CMOS technology
• 16 bit memory organization
- 6 x 16 bit organization (93C06)
- 64 x 16 bit organization (93C46)
• Single 5 volt only operation
• Self-timed ERASE and WRITE cycles
• Automatic ERASE before WRITE
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data Retention > 200 years
• 8-pin DIP or SOIC package
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
• 2 ms program cycle time
DESCRIPTION
The Microchip Technology Inc. 93C06/46 family of
Serial Electrically Erasable PROMs are configured in a
x16 organization. Advanced CMOS technology makes
these devices ideal for low-power non-volatile memory
applications. The 93C06/46 is available in the standard
8-pin DIP and surface mount SOIC packages. The
93C46X comes as SOIC only.
These devices offer fast (1 ms) byte write and extended
(-40˚C to +125˚C) temperature operation. It is recom-
mended that all other applications use Microchip’s
93LC46.
PACKAGE TYPE
DIP
CS 1
8 VCC
CLK 2 93C06 7 NC
93C46
DI 3
6 NC
DO 4
5 VSS
SOIC
CS
CLK
DI
DO
18
27
93C06
3 93C46 6
45
VCC
NC
NC
VSS
NC
VCC
CS
CLK
18
27
93C46X
36
45
NC
VSS
DO
DI
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
ADDRESS
DECODER
DATA REGISTER
DI
MODE
DECODE
CS LOGIC
CLOCK
CLK
GENERATOR
OUTPUT
BUFFER
DO
© 1995 Microchip Technology Inc.
DS11179C-page 1
1 page  
93C06/46
3.4 READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
bit (logical 0) precedes the 16-bit output string. The
output data changes during the HIGH state of the sys-
tem clock (CLK). The dummy bit is output TPD after
the positive edge of CLK, which was used to clock in
the last address bit (A0). Therefore, care must be
taken if DI and DO are connected together as a bus
contention will occur for one clock cycle if A0 has been
a one.
DO will go into HIGH-Z mode with the positive edge of
the next CLK cycle. This follows the output of the last
data bit D0 or the low going edge of CS, which ever
occurs first.
DO remains stable between CLK cycles for an unlim-
ited time as long as CS stays HIGH.
The most significant data bit (D15) is always output
first, followed by the lower significant bits (D14 - D0).
FIGURE 3-1: READ MODE
CLK
3.5 WRITE Mode
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. The most
significant data bit (D15) has to be clocked in first, fol-
lowed by the lower significant data bits (D14 – D0). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an
automatic ERASE cycle on the specified address
before the data are written. The WRITE cycle is com-
pletely self-timed and commences automatically after
the rising edge of the CLK for the last data bit (D0).
The WRITE cycle takes 2 ms maximum.
T CSL
CS
SB OP1 OP2 A5 A4 A3
A0
DI
11 0
T PD
T DDZ
DO
HIGH - Z
0 D15
D0
FIGURE 3-2: WRITE MODE
CLK
CS
SB OP1 OP2 A5 A4 A3
A0 D15
DI
10 1
DO HIGH - Z
NEW INSTRUCTION
OR STANDBY (CS = 0)
TCSL
TCSL
STATUS
CHECK
D0
TSV
BSY RDY
TWC
NEW INSTRUCTION
OR STANDBY (CS = 0)
TDDZ
© 1995 Microchip Technology Inc.
DS11179C-page 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 93C06.PDF ] | |
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