NTE3880 PDF даташит
Спецификация NTE3880 изготовлена «NTE» и имеет функцию, называемую «Integrated Circuit NMOS / 8-Bit Microprocessor (MPU) / 4MHz». |
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Детали детали
Номер произв | NTE3880 |
Описание | Integrated Circuit NMOS / 8-Bit Microprocessor (MPU) / 4MHz |
Производители | NTE |
логотип |
5 Pages
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NTE3880
Integrated Circuit
NMOS, 8–Bit Microprocessor (MPU), 4MHz
Description:
The NTE3880 is a third generation single chip microprocessor with unrivaled computational power.
This increased computational power results in higher system through–put and more efficient memory
utilization when compared to second generation microprocessors. In addition it is very easy to imple-
ment into a system because of it’s single voltage requirement plus all output signals are fully decoded
and timed to control standard memory or peripheral circuits. The circuit is implemented using an N–
channel, ion implanted, silicon gate MOS process.
This device has an internal register configuration which contains 208 bits of Read/Write memory that
are accessible to the programmer. The registers include two sets of six general purpose registers that
may be used individually as 8–bit registers or as 16–bit register pairs. There are also two sets of accu-
mulator and flag registers. The programmer has access to either set of main or alternate registers
through a group of exchange instructions. This alternate set allows foreground/background mode of
operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16–bit
stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine
nesting and simplification of many types of data handling.
The two 16–bit index registers allow tabular data manipulation and easy implementation of relocat-
able code. The Refresh register provides for automatic, totally transparent refresh of external dynam-
ic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of
a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits
of the pointer. An indirect call is then made to this service address.
Features:
D Single Chip, N–Channel Silicon Gate
D 158 Instructions – Includes all 78 of the 8080A Instructions with Total Software Compatibility. New
Instructions Include 4–, 8– and 16–Bit Operations with more useful Addressing Modes such as
Indexed, Bit and Relative
D 17 Internal Registers
D Three Modes of Fast Interrupt Response plus a Non–Maskable Interrupt
D Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic
D 1.0µs Instruction Execution Speed
D Single 5VDC Supply and Single–Phase 5V Clock
D Out–Performs any other Single–Phase 5V Clock
D All Pins TTL Compatible
D Built–In Dynamic RAM Refresh Circuitry
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Absolute Maximum Ratings:
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only functional operation of the device at these
or any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Tri–State Output Leakage Current in Float
Tri–State Output Leakage Current in Float
Data Bus Leakage Current in Input Mode
VILC
VIHC
VIL
VIH
VOL
VOH
ICC
IL1
ILOH
ILOL
ILD
IOL = 1.8mA
IOH = –250µA
VIN = 0 to VCC
VOUT = 2.4 to VCC
VOUT = 0.4V
0 ≤ VIN ≤ VCC
–0.3 – 0.80 V
VCC–0.6 – VCC+3 V
–0.3 – 0.8 V
2.0 – VCC V
– – 0.4 V
2.4 – – V
– 90 200 mA
– – 10 µA
– – 10 µA
– – –10 µA
– – ±10 µA
Capacitance: (TA = +25°C, f = 1MHz, unmeasured pins to GND unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Clock Capacitance
Input Capacitance
Output Capacitance
Cφ
CIN
COUT
– – 35 pF
––
5 pF
– – 10 pF
AC Characteristics: (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified)
Parameter
Symbol Signal Test Conditions Min Typ Max Unit
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Width, Clock Low
Clock Rise and Fall Time
Address Output Delay
Data to Float
Address Stable Prior to MRFQ (Memory Cycle)
Address Stable Prior to IOFQ, RD or WR (I/O Cycle)
Address Stable from RD, WR, IORQ, or MREQ
Address Stable from RD or WR During Float
tc
tw (φH)
tw (φL)
tr, tf
tD (AD)
tF (AD)
tacm
taci
tca
tcaf
φ
A0–15 CL = 50pF
25 – Note 2 µs
110 – Note 3 ns
110 – 2000 ns
– – 30 ns
– – 110 ns
– – 90 ns
Note 4 – – ns
Note 5 – – ns
Note 6 – – ns
Note 7 – – ns
Note 2. tc = tw (φH) + tw (φL) + tr + tf.
Note 3. Although static by design, testing guarantees tw (φH) of 200µs maximum.
Note 4. tacm = tw (φH) + tf–65.
Note 5. taci = tc–70.
Note 6. tca = tw (φL) + tr–50.
Note 7. tcaf = tw (φL) + tr–45.
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AC Characteristics (Cont’d): (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified)
Parameter
Symbol Signal Test Conditions Min Typ Max Unit
Data Output Delay
Delay to Float During Write Cycle
tD (D)
tF (D)
D0–7 CL = 50pF
– – 150 ns
– – 90 ns
Data Setup Time to Rising Edge of Clock
During M1 Cycle
Data Setup Time to falling Edge of Clock
During M2 to M5
Data Stable Prior to WR (Memory Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Any Hold Time for Setup Time
MREQ Delay From Falling Edge of Clock,
MREQ Low
tSφ (D)
tdcm
tdci
tcdf
tH
tDLφ (MR)
MREQ CL = 50pF
35 –
50 –
Note 8
Note 9
Note 10
–
–
–
–
–
–
–
– ns
– ns
– ns
– ns
– ns
0 ns
85 ns
MREQ Delay From Rising Edge of Clock, tDHφ (MR)
MREQ High
– – 85 ns
MREQ Delay From Falling Edge of Clock,
MREQ High
– – 85 ns
Pulse Width, MREQ Low
Pulse Width, MREQ High
IORQ Delay From Rising Edge of Clock
IORQ Low
tw (MRL)
tw (MRH)
tDLφ (IR)
IORQ CL = 50pF
Note 11
Note 12
–
–
–
–
– ns
– ns
75 ns
IORQ Delay From Falling Edge of Clock
IORQ Low
– – 85 ns
IORQ Delay From Rising Edge of Clock
IORQ High
tDHφ (IR)
– – 85 ns
IORQ Delay From Falling Edge of Clock
IORQ High
– – 85 ns
RD Delay From Rising Edge of Clock,
RD Low
tDLφ (RD) RD CL = 50pF
– – 85 ns
RD Delay From Falling Edge of Clock,
RD Low
– – 95 ns
RD Delay From Rising Edge of Clock,
RD High
tDHφ (RD)
– – 85 ns
RD Delay From Falling Edge of Clock,
RD High
– – 85 ns
WR Delay From Rising Edge of Clock,
WR Low
tDLφ (WR) WR CL = 50pF
– – 65 ns
WR Delay From Falling Edge of Clock,
WR Low
– – 80 ns
WR Delay From Falling Edge of Clock,
WR High
tDHφ (WR)
– – 80 ns
Pulse Width, WR Low
tw (WRL)
Note 13 –
– ns
Note 8. tdcm = tc–170.
Note 9. tdci = tw (φL) + tr–170.
Note10. tcdf = tw (φL) + tr–70.
Note 11. tw (MRL) = tc–30.
Note12. tw (MRH) = tw (φH) + tr–20.
Note13. tw (WRL) = tc–30.
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