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PDF NTE7134 Data sheet ( Hoja de datos )
| Número de pieza | NTE7134 | |
| Descripción | Integrated Circuit Horizontal and Vertical Deflection Controller for Monitors | |
| Fabricantes | NTE Electronics | |
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NTE7134
Integrated Circuit
Horizontal and Vertical Deflection Controller
for Monitors
Description:
The NTE7134 is a high performance and efficient solution for autosync monitors in a 32–Lead DIP
type package. The concept is fully DC controllable and can be used in applications with a microcon-
troller and stand–alone in rock bottom solutions.
This device provides synchronization processing, H + V synchronization with full autosync capability,
and very short setting times after mode changes. External power components are givena great deal
of protection. The IC generates the drive waveforms for DC–coupled vertical boosters.
The NTE7134 provides ectended functions e.g. as a flexible SMPS block and an extensive set of ge-
ometry control facilities, providing excellent picture quality.
Features:
Concept Features
D Full Horizontal (H) Plus Vertical (V) Autosync Capability
D Completely DC Controllable for Analog and Digital Concepts
D Excellent Geometry Control Functions (e.g. Automatic Correction of East–West (EW) Parabola
During Adjustment of Vertical Size and Vertical Shift)
D Felxible Switched Mode Power Supply (SMPS) Function Block for Feedback and Feed Forward
Converters.
D X–Ray Protection
D Start–Up and Switch–Off Sequences for safe Operation of All Power Components
D Very Good Vertical Linearity
D Internal Supply Voltage Stabilization
Synchronization Inputs
D Can Handle All Sync Signals (Horizontal, Vertical, Composite and Sync–On–Video)
D Combined Output for Video Clamping, Vertical Blanking and Protection Blanking
D Start of Video Clamping Pulses Externally Selectable
Horizontal Section
D Extremely Low Jitter
D Frequency Locked Loop for Smooth Catching of Line Frequrncy
D Simple Frequency Preset of fmin and fmax by External Resistors
D DC Controllable Wdie Range Linear Picture Position
D Soft Start for Horizontal Driver
Vertical Section
D Vertical Amplitude Independent of Frequency
D DC Controllable Picture Height, Picture Position and S–Correction
D Differential Current Outputs for DC Coupling to Vertical Booster
1 page  
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Adjustment of Horizontal Picture Position (Cont’d)
Reference Voltage at Input
Picture Shift is Centered if
HPOS (Pin30) is Forced to GND
Vref(HPOS)
Voff(HPOS)
Note 7
– 5.1 –
V
0 – 0.1 V
Horizontal Oscillator [HCAP (Pin29) and HREF (Pin28)]
Free–Running Frequency Without PLL1
Action (For Testing Only)
Spread of Free–Running Frequency
(Excluding Spread of External
Components)
Temperature Coefficient of
Free–Running Frequency
fH(0)
∆fH(0)
RHBUF = ∞, RHREF = 2.4kΩ,
CHCAP = 10nF, Note 5
30.53 31.45 32.39
– – ±3.0
kHz
%
TC –100 – +100 10–6/K
Maximum Oscillator Frequency
fH(max)
Voltage at Input for Reference Current
VHREF
PLL2 Phase Detector [HFLB (Pin1) and HPPL2 (Pin31)]
– – 130 kHz
2.43 2.55 2.68 V
PLL2 Control (Advance of Horizontal
Drive with Respect to Middle of
Horizontal Flyback)
∆φPLL2
Maximum Advance
Minimum Advance
36 – – %
– 7–%
Delay Between Middle of Horizontal
Sync and Middle of Horizontal
Flyback
td(HFLB) HPOS (Pin30) Grounded
– 200 –
ns
Maximum Voltage for PLL2 Protection
Mode/Soft Start
VPROT(HPLL2)
– 4.4 –
V
Charge Current for External Capacitor
During Soft Start
Icharge(HPLL2) VHPLL2 < 3.7V
– 15 – µA
Horizontal Flyback Input [HFLB (Pin1)]
Positive Clamping Level
Negative Clamping Level
Positive Clamping Current
Negative Clamping Current
VHFLB
IHFLB
IHFLB = 5mA
IHFLB = –1mA
– 5.5 –
– –0.75 –
– –6
– – –2
V
V
mA
mA
Slicing Level
VHFLB
Output Stage for Line Driver Pulses [HDRV (Pin7)]
– 2.8 –
V
Open Collector Output Stage
Saturation Voltage
Output Leakage Current
Automatic Variation of Duty Factor
VHDRV
Ileakage(HDRV)
IHDRV = 20mA
IHDRV = 60mA
VHDRV = 16V
– – 0.3 V
– – 0.8 V
– – 10 µA
Relative tOFF Time of HDRV Output
tHDRV(OFF)/tH IHDRV = 20mA, fH = 31.45kHz 42.0 45.0 48.0
Measured at VHDRV = 3V,
HDRV Duty Factor is Determined by
IHDRV = 20mA, fH = 57kHz
45.0 46.3 47.7
the Relation IHREF/IVREF
IHDRV = 20mA, fH = 90kHz
46.6 48.0 49.4
%
%
%
Note 5. Oscillator frequency is fmin when no sync signal is present (no continuous blanking at Pin16).
Note 7. Input resistance at HPOS (Pin30):
RHPOS =
kT
q
x
1
IHPOS
5 Page 
Functional Description (Cont’d):
Frequency–Locked Loop
The frequency–locked loop can lock the horizontal oscillator over a wide frequency range. This is
achieved by a combined search and PLL operation. The frequency range is preset by two external
resistors and the recommended ratio is
fmin
fmax
=
1
3.5
Larger ranges are possible by extended applications.
Without a horizontal sync signal the oscillator will be free–running at fmin. Any change of sync condi-
tions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal
sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1
control currents are switched off immediately. Then the internal frequency detector starts tuning the
oscillator. Very small DC currents at HPLL1 (Pin26) are used to perform this tuning with a well defined
change rate. When coincidence between horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation. This operation ensures a smooth tuning and
avoids fast changes of horizontal frequency during catching.
In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed inter-
nally to HBUF (Pin27) via a sample–and–hold and buffer stage. The sample–and–hold stage re-
moves all disturbances caused by horizontal sync or composite vertical sync from the buffered volt-
age. An external resistor from HBUF to HREF defines the frequency range.
See also hints for locking procedure in Note 2 of the “Electrical Characteristics” section of this data
sheet.
PLL1 Phase Detector
The phase detector is a standard type using switched current sources. The middle of the horizontal
sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL1 loop filter is connected
to HPLL (Pin26).
Horizontal Oscillator
This oscillator is a relaxation type and requires a fixed capacitor of 10nF at HCAP (Pin29). For opti-
mum jitter performance the value of 10nF must not be changed.
The maximum oscillator frequency is determined by a resistor from HREF to GND. A resistor from
HREF to HBUF defines the frequency range.
The reference current at HREF also defines the integration time constant of the vertical sync integration.
Calculation of Line Frequency Range
First the oscillator frequencies fmin and fmax have to be calculated. This is achieved by adding the
spread of the relevant components to the highest and lowest sync frequencies fS(min) and fS(max). The
oscillator is driven by the difference of the currents in RHREF and RHBUF. At the highest oscillator fre-
quency RHBUF does not contribute to the spread. The spread will increase towards lower frequencies
due to the contribution of RHBUF. It is also dependent on the ratio
fS(max)
fS(min)
The following example is a 31.45 to 64kHz application:
ns =
fS(max)
fS(min)
=
64kHz
31.45kHz
= 2.04
Table 1. Calculation of total spread
spread of:
for fmax
IC 3%
for fmin
3%
CHCAP
RHREF
RHREF. RHBUF
Total
2% 2%
1% –
– 1% x (2.3 x ns –1)
6% 8,69%
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NTE7134.PDF ] | |
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