NTE7156 PDF даташит
Спецификация NTE7156 изготовлена «NTE Electronics» и имеет функцию, называемую «Integrated Circuit DC-Coupled Vertical Deflection Circuit». |
|
Детали детали
Номер произв | NTE7156 |
Описание | Integrated Circuit DC-Coupled Vertical Deflection Circuit |
Производители | NTE Electronics |
логотип |
4 Pages
No Preview Available ! |
NTE7156
Integrated Circuit
DC–Coupled Vertical Deflection Circuit
Description:
The NTE7156 is a power circuit in a 9–Lead SIP type package designed for use in 90° and 110° color
deflection systems for field frequencies of 50Hz to 120Hz. This device provides a DC driven vertical
deflection output circuit, operating as a highly efficient class G system.
Features:
D Few External Components
D Highly Efficient Fully DC–Coupled Vertical Output Bridge Circuit
D Vertical Flyback Switch
D Guard Circuit
D Protection Aaginst:
– Short–Circuit of the Output Pins (7 and 4)
– Short–Circuit of the Output Pins to VP
D Temperature Protection
D High EMC Immunity Because of Common Mode Inputs
D A Guard Signal in Zoom Mode
Absolute Maximum Ratings:
DC Supply
Supply Voltage, VP
Non–Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Flyback Supply Voltage, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V
Note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V
Vertical Circuit
Output Current (Peak–to–Peak Value, Note 2), IO(P–P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A
Output Voltage (Pin7), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V
Note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62V
Flyback Switch
Peak Output Current, IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15A
Thermal Data
Virtual Junction Temperature, TVJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +75°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C
Thermal Resistance, Virtual Junction–to–Ambient, RthVJ–C . . . . . . . . . . . . . . . . . . . . . . . . . . . 40K/W
Thermal Resistance, Virtual Junction–to–Case, RthVJ–A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4K/W
Short–Circuit Time (Note 3), tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Hour
Note 1. A flyback supply voltage of > 50V up to 60V is allowed in application. A 22–nF capacititor
in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be con-
nected between Pin7 and GND. The decoupling capacitor of VFB has to be connected be-
tween Pin6 and Pin3. This supply voltage line must have a resistance of 33Ω.
Note 2. IO maximum determined by current protection.
Note 3. Up to VP = 18V.
No Preview Available ! |
Electrical Characteristics: (VP = 17.5V, TA = +25°C, VFB = 45V, fi = 50Hz, II(sb) = 400µA
unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max
DC Supply
Operating Supply Voltage
Flyback Supply Voltage
Supply Current
Vertical Circuit
VP
VFB
Note 1
IP No Load, No Signal
9 – 25
VP – 50
VP – 60
– 30 55
Output Voltage Swing (Scan)
Linearity Error
Output Voltage Swing (Flyback)
VO(A) – VO(B)
Forward Voltage of the Internal
Efficiency Diode (VO(A) – VFB)
Output Offset Current
Offset Voltage at the Input of the
Feedback Amplifier (VI(fb) – VO(B))
DC Output Voltage
Open Loop Voltage Gain (V7–4/V1–2)
Open Loop Voltage Gain
(V7–4/V9–4, V1–2 = 0)
Voltage Ratio V1–2/V9–4
Frequency Response (–3dB)
Current Gain (IO/Idiff)
Current Gain Drift as a Function
of Temperature
VO
LE
VO
VDF
|IOS|
∆VOS T
VO(A)
GVO
VR
fres
GI
∆GC T
Idiff = 0.6mA(P–P), Vdiff = 1.8V(P–P),
IO = 3A(P–P)
IO = 3A(P–P), Note 4
IO = 50mA(P–P), Note 4
Idiff = 0.3mA, IO = 1.5A
IO = –1.5A, Idiff = 0.3mA
Idiff = 0, II(sb) = 50µA to 500µA
Idiff = 0
Idiff = 0, Note 5
Note 6, Note 7
Note 6
Open Loop, Note 8
19.8 –
–
–13
–13
– 39 –
– – 1.5
– – 30
– – 72
–8–
– 80 –
– 80 –
–0–
– 40 –
– 5000 –
– – 10–4
Signal Bias Current
Flyback Supply Current
Power Supply Ripple Rejection
II(sb)
IFB
PSRR
During Scan
Note 9
50 400 500
– – 100
– 80 –
DC Input Voltage
Common Mode Input Voltage
Input Bias Current
Common Mode Output Current
Guard Circuit
VI(DC)
VI(CM)
Ibias
IO(CM)
II(sb) = 0
II(sb) = 0
∆II(sub) = 300µA(P–P), fi = 50Hz,
Idiff = 0
– 2.7 –
0 – 1.6
– 0.1 0.5
– 0.2 –
Output Current
Output Voltage on Pin8
Allowable Voltage on Pin8
IO Not Active, VO(guard) = 0V
Active, VO(guard) = 3.6V
VO(guard) IO = 100µA
Maximum Leakage Current =
10µA
– – 50
1.0 – 2.5
4.6 – 5.5
– – 40
Unit
V
V
V
mA
V
%
%
V
V
mA
µV/K
V
dB
dB
dB
Hz
K
µA
µA
dB
V
V
µA
mA
µA
mA
V
V
No Preview Available ! |
Notes:
Note 1. A flyback supply voltage of > 50V up to 60V is allowed in application. A 22–nF capacititor
in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be con-
nected between Pin7 and GND. The decoupling capacitor of VFB has to be connected be-
tween Pin6 and Pin3. This supply voltage line must have a resistance of 33Ω.
Note 4. The linearity error is measured without S–correction and based on the same measurement
principle as performed on the screen. The measuring method is as follows:
Divide the output signal I4 – I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure
the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending
with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error
for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below:
LEAB =
ak – a(k + 1)
aavg
Note 5. Referenced to VP.
; LEAB =
amax – amin
aavg
Note 6. The V values within formulae relate to voltages at or across relative pin numbers, i.e.
V7–4/V1–2 = voltage value across Pin7 and Pin4 divided by voltage value across Pin1 and Pin2.
Note 7. V9–4 AC short–circuited.
Note 8. Frequency response V7–4/V9–4 is equal to frequency response V7–4/V1–2.
Note 9. At V(ripple) = 500mV eff; measured across RM; fi = 50Hz.
Pin Connection Diagram
(Front View)
9 VI(fb)
8 VO(guard)
7 VO(A)
6 VFB
5 GND
4 VO(B)
3 VP
2 Idrive(neg)
1 Idrive(pos)
Скачать PDF:
[ NTE7156.PDF Даташит ]
Номер в каталоге | Описание | Производители |
NTE715 | Integrated Circuit TV Chroma IF Amp | NTE Electronics |
NTE7150 | Integrated Circuit Video / Chroma / and Sync. Signal Processing Circuit for PAL/NTSC/SECAM System Color Televisions | NTE Electronics |
NTE7151 | Integrated Circuit I2C Bus Control NTSC 1-Chip Color TV IC | NTE Electronics |
NTE7152 | Integrated Circuit Hybrid Switching Voltage Regulator | NTE Electronics |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |