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PDF NTE849 Data sheet ( Hoja de datos )
| Número de pieza | NTE849 | |
| Descripción | Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System | |
| Fabricantes | NTE Electronics | |
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NTE849
Integrated Circuit
TV Horizontal/Vertical Countdown
Digital Sync System
Description:
The NTE849 is an integrated circuit in a 14–Lead DIP type package designed for use in TV horizontal/
vetical countdown digital sync systems. In some video playback units, there are incorrect frequency
relationships between horizontal and field frequencies. Automatic forced asynchronous mode elimi-
nates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.
Automatic standard mode occurs upon detection of nine or more equalizing pulses during a six–line–
width vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and
internal counter output. Standard mode is retained for seven fields of missing or mutilated vertical
sync pulses.
If two or more noise pulses are detected at Pin12 during a 384–line active scan time, a noise detector
reverts the system to standard mode at the next field of coincidence (without seven fields of coinci-
dene delay). Thus, the unit stays in standard mode during tuner channel changes.
An automatic mode–recognition system places the unit in standard mode for NTSC signals or into
non–synchronous mode for non–standard sync signals.
An external oscillator (NTE701) supplies an input to Pin9 that is 32 times the horizontal rate. An inter-
nal divide–by–16 counter converts this input (32fH) to 2fH for use elsewhere. This 32fH signal is further
divided to fH, which is available at Pin11 to drive the horizontal deflection circuits. A divide–by–525
counter further divides the 2fH signal to generate the vertical ramp generator timing pulses and the
vertical blanking pulse.
A phasing circuit (part of the mode recognition and vertical regeneration circuits) insures that the 525
counter is reset in coincidence with the vertical sync. It does this by comparing the internally gener-
ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12. The automatic
mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the non–
synchronous mode for non–standard sync signals such as video games. An input control signal (or
no connection) at Pin8 places the NTE849 into non–synchronous operation.
A phasing and timing logic circuit checks to see if the line counter is in sync with the IV signal at Pin12.
Seven consecutive fields of in–phase coincidence with the IV signal are needed to achieve standard
mode in unless two or more noise pulses are de–detected at input Pin12 during the active scan time.
In this case, normal mode will be acquired in one field.
1 page  
Notes (Cont’d):
Note14. Frequency at Pin9 (clock) divided by frequency at Pin3 (ramp control).
Note15. Initilize or repeat initilization procedure before doing this test.
Note16. Apply a pulse 1 clock wide, 7808 clocks after first positive transition at Pin3.
Note17. Default count determined by 684 x 16(H) = 10944.
Note18. Sync serrations = 9.
Note19. Hold–off count determined by 492 x 16(H) = 7872.
Note20. Number of clocks occurring within ramp gate period.
Note21. Number of clocks occurring during the blanking gate period.
Note22. This series of tests checks the mode recognition circuits. The first test after initialization ap-
plies 9 serrations at the sync input pin. The IC should go to the synchronous count ratio of
8400. During the next seven fields only 8 serrations are applied. The NTE849 should main-
tain the synchronous count ratio of 8400 for the first six fields. At the seventh field the
NTE849 should go to default count of 10944. The test concludes with a 9–serration input.
The NTE849 should revert to a synchronous count of 8400.
Note23. This test checks the operation of the out–of–sync detector by applying out–of–phase sync
pulses to Pin12. The NTE849 will count eight fields before resetting to the sync pulse.
Note24. Initialize by 8364 sync for eight fields before test.
Note25. This test verifies the operation of the fast resync performance by simulating a noise pulse
(5 to 50 clocks wide) applied to the IV pin 4000 to 6000 clocks (8ms to 12ms) after IV sync.
Initialize to non–sync mode before performing this test. The IC should resync in the next field
and be maintained for the standard confidence count of seven fields.
Pin Connection Diagram
VCC 1
Vertical Height 2
Ramp Charge Cap 3
External Bias Load 4
Yoke Feedback 5
Vertical Driver 6
Vertical Blank Output 7
14 GND
13 Comp Sync Input
12 Vertical Sync Input
11 To Horizontal Deflection Circuit
10 Async Time Constant
9 32 x Horizontal
8 Mode Select
14 8
17
.785 (19.95)
Max
.200 (5.08)
Max
.300
(7.62)
.100 (2.45)
.600 (15.24)
.099 (2.5) Min
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet NTE849.PDF ] | |
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