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N28F001BX-T70 PDF даташит

Спецификация N28F001BX-T70 изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY».

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Номер произв N28F001BX-T70
Описание 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
Производители Intel Corporation
логотип Intel Corporation логотип 

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N28F001BX-T70 Даташит, Описание, Даташиты
1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y High-Integration Blocked Architecture
One 8 KB Boot Block w Lock Out
Two 4 KB Parameter Blocks
One 112 KB Main Block
Y 100 000 Erase Program Cycles Per
Block
Y Simplified Program and Erase
Automated Algorithms via On-Chip
Write State Machine (WSM)
Y SRAM-Compatible Write Interface
Y Deep Power-Down Mode
0 05 mA ICC Typical
0 8 mA IPP Typical
Y 12 0V g5% VPP
Y High-Performance Read
70 75 ns 90 ns 120 ns 150 ns
Maximum Access Time
5 0V g10% VCC
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Advanced Packaging JEDEC Pinouts
32-Pin PDIP
32-Lead PLCC TSOP
Y ETOXTM II Nonvolatile Flash
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s
MCS -186 family 80286 i386TM i486TM i860TM and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290406-007









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N28F001BX-T70 Даташит, Описание, Даташиты
28F001BX-T 28F001BX-B
290406 – 1
Figure 1 28F001BX Block Diagram
Table 1 Pin Description
Symbol Type
Name and Function
A0 – A16
INPUT ADDRESS INPUTS for memory addresses Addresses are internally latched during
a write cycle
DQ0 – DQ7
INPUT
OUTPUT
DATA INPUTS OUTPUTS Inputs data and commands during memory write
cycles outputs data during memory Status Register and Identifier read cycles The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled Data is internally latched during a write cycle
CE INPUT CHIP ENABLE Activates the device’s control logic input buffers decoders and
sense amplifiers CE is active low CE high deselects the memory device and
reduces power consumption to standby levels
RP INPUT POWERDOWN Puts the device in deep powerdown mode RP is active low
RP high gates normal operation RP e VHH allows programming of the boot
block RP also locks out erase or write operations when active low providing data
protection during power transitions RP active resets internal automation Exit
from deep powerdown sets device to Read Array mode
OE INPUT OUTPUT ENABLE Gates the device’s outputs through the data buffers during a
read cycle OE is active low OE e VHH (pulsed) allows programming of the
boot block
WE INPUT WRITE ENABLE Controls writes to the Command Register and array blocks WE
is active low Addresses and data are latched on the rising edge of the WE pulse
VPP ERASE PROGRAM POWER SUPPLY for erasing blocks of the array or
programming bytes of each block Note With VPP k VPPL max memory contents
cannot be altered
VCC
GND
DEVICE POWER SUPPLY (5V g10%)
GROUND
2









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N28F001BX-T70 Даташит, Описание, Даташиты
28F010
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
28F001BX-T 28F001BX-B
28F010
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
290406 – 2
Figure 2 DIP Pin Configuration
28F010
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 3 TSOP Lead Configuration
290406 – 3
28F010
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
3










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Номер в каталогеОписаниеПроизводители
N28F001BX-T701-MBIT (128K x 8) BOOT BLOCK FLASH MEMORYIntel Corporation
Intel Corporation

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