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N74F552D PDF даташит

Спецификация N74F552D изготовлена ​​​​«Philips» и имеет функцию, называемую «Octal registered transceiver with parity and flags 3-State».

Детали детали

Номер произв N74F552D
Описание Octal registered transceiver with parity and flags 3-State
Производители Philips
логотип Philips логотип 

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N74F552D Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F552
Octal registered transceiver with parity
and flags (3-State)
Product specification
IC15 Data Handbook
1991 Jan 02
Philips
Semiconductors









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N74F552D Даташит, Описание, Даташиты
Philips Semiconductors
Octal registered transceiver with parity and flags (3-State)
Product specification
74F552
FEATURES
8-bit bidirectional I/O port with handshake
Register status flag flip-flops
Separate clock enable and output enable
Parity generation and parity check
B outputs and parity output sink 64mA
DESCRIPTION
The 74F522 Octal Registered Transceiver contains two 8-bit
registers for temporary storage of data flowing in either direction.
Each register has its own clock (CPR, CPS) and Clock Enable
(CER, CES) inputs, as well as a flag flip-flop that is set automatically
as the register is loaded. The flag output will be reset when the
Output Enable returns to High after reading the output port. Each
register has a separate Output Enable (OEAS, OEBR) for its 3-State
buffer. The separate Clocks, Flags and Enables provide
considerable flexibility as I/O ports for demand-response data
transfer. When data is transferred from the A port to the B port, a
parity bit is generated. On the other hand, when data is transferred
from the B port to the A port, the parity of input data on B0–B7 is
checked.
TYPE
74F552
TYPICAL fMAX
85MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
120mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
28-Pin Plastic DIP
(600mil)
N74F552N
SOT117-2
28-Pin Plastic SOL
N74F552D
SOT136-1
LOGIC SYMBOL
18 17 16 15 14 13 12 11
6
7
21
20
19
5
VCC = Pin 8
GND = Pin 22
A0 A1 A2 A3 A4 A5 A6 A7
CPR
CER
CES
CPS
OEAS
PARITY
FS
FR
ERROR
OEBR
B0 B1 B2 B3 B4 B5 B6 B7
23
10
24
9
25 26 27 28 1 2 3 4
SF01041
PIN CONFIGURATION
B4 1
B5 2
B6 3
B7 4
OEBR 5
CPR 6
CER 7
VCC 8
ERROR 9
FS 10
A7 11
A6 12
A5 13
A4 14
28 B3
27 B2
26 B1
25 B0
24 FR
23 PARITY
22 GND
21 CES
20 CPS
19 OEAS
18 A0
17 A1
16 A2
15 A3
SF01039
LOGIC SYMBOL (IEEE/IEC)
XCVR
6 1C2
5,6
7 EN1’
5,6
5 EN6
20 6C4
6
21
EN3
Z7 6,7
19 EN6
5
23
9
10
14
18
3,4,6
1,2,6
25
17 26
16 27
15 28
14 1
13 2
12 3
11 4
SF01040
1991 Jan 02
2 853–1098 01347









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N74F552D Даташит, Описание, Даташиты
Philips Semiconductors
Octal registered transceiver with parity and flags (3-State)
Product specification
74F552
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
A0–A7
A Data inputs
3.5/1.0
B0–B7
B Data inputs
3.5/1.0
CPR
R registers clock input (active rising edge)
1.0/1.0
CPS
S registers clock input (active rising edge)
1.0/1.0
CER
R registers clock Enable input (active Low)
1.0/1.0
CES
S registers clock Enable input (active Low)
1.0/1.0
OEBR
A-to-B Output Enable input (active Low)
and clear FS output (active Low)
1.0/2.0
OEAS
B-to-A Output Enable input (active Low)
and clear FR output (active Low)
1.0/2.0
PARITY
Parity bit transceiver input
Parity bit transceiver output
3.5/1.0
750/106.7
ERROR
Parity check output (active Low)
50/33.3
A0–A7
A Data outputs
150/40
B0–B7
B Data outputs
750/106.7
FR A-to-B Status Flag output (active High)
50/33.3
FS B-to-A Status Flag output (active High)
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
50/33.3
LOAD VALUE
HIGH/LOW
70µA/0.6mA
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
70µA/0.6mA
15mA/64mA
1.0mA/20mA
3.0mA/24mA
15mA/64mA
1.0mA/20mA
1.0mA/20mA
FUNCTIONAL DESCRIPTION
Data applied to the A inputs are entered and stored on the rising
edge of the CPR clock pulse, provided that the CER is Low;
simultaneously, the status flip-flop is set and the A-to-B flag (FR)
output goes High. As the CER returns to High, the data will be held
in R register. This data entered from the A inputs will appear at the B
port I/O pins after the OEBR has gone Low. When OEBR is Low, a
parity bit appears at the PARITY pin, which will be set High when
there is an even number of 1s or all 0s at the Q outputs of the R
register. After the data is assimilated, the receiving system clears
the flag FR, by changing the signal at the OEBR pin from Low to
High. Data flow from B-to-A proceeds in the same manner described
for A-to-B flow. A Low at the CES pin and a Low-to-High transition at
the CPS pin enters the B input data and the parity input data into the
S register and the parity register respectively and set the flag output
FS to High. A Low signal at the OEAS pin enables the A port I/O
pins and a Low-to-High transition of the OEAS signal clears the FS
flag. When OEAS is Low, the parity check output ERROR will be
High if there is an odd number of 1s at the Q outputs of the S
register and the parity register.
R or S REGISTER FUNCTION TABLE
INPUTS
OUTPUTS
An or Bn CPX CEX INTERNAL Q
X XH
NC
L L
H L
L
H
X L
H = High voltage level
L = Low voltage level
NC= No change
X = Don’t care
X = R or S for CPX and CEX
= Low-to-High transition
= Not Low-to-High transition
NC
OPERATING
MODE
Hold data
Load data
Keep old data
OUTPUT CONTROL TABLE
INPUT
OEXX
OUTPUTS
INTERNAL Q
An or Bn
HX
Z
LL
LH
H = High voltage level
L = Low voltage level
X = Don’t care
XX= AS or BR
Z = High impedance “off” state
L
H
OPERATING
MODE
Disable outputs
Enable outpus
1991 Jan 02
3










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Номер в каталогеОписаниеПроизводители
N74F552DOctal registered transceiver with parity and flags 3-StatePhilips
Philips
N74F552NOctal registered transceiver with parity and flags 3-StatePhilips
Philips

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