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N74F598D PDF даташит

Спецификация N74F598D изготовлена ​​​​«Philips» и имеет функцию, называемую «8-bit shift register with input storage registers 3-State».

Детали детали

Номер произв N74F598D
Описание 8-bit shift register with input storage registers 3-State
Производители Philips
логотип Philips логотип 

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N74F598D Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F598
8-bit shift register with input storage
registers (3-State)
Product specification
IC15 Data Handbook
1991 Oct 21
Philips
Semiconductors









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N74F598D Даташит, Описание, Даташиты
Philips Semiconductors
8-bit shift register with input storage registers (3-State)
Product specification
74F598
FEATURES
High impedance PNP base input for reduced loading (20µA in
High and Low states)
8–bit parallel storage register
Shift register has asynchronous direct overriding reset
Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High.
Guaranteed shift frequency DC to 105MHz
Parallel 3–State I/O storage register inputs and shift register
parallel outputs
DESCRIPTION
The 74F598 consists of an 8–bit storage register feeding a
parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both
the storage register and shift register have positive edge–triggered
clocks. The shift register has asynchronous reset and when SHCP
is Low, it has asynchronous load.
The shift register load function has been modified to load when both
SHLD and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD is High.
TYPE TYPICAL SHCP fmax
74F598
100MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
75mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20–pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F598N
20–pin plastic SOL
N74F598D
PKG DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
I/On Parallel data input
Ds0, Ds1 Serial data inputs
SHCP
Shift register clock pulse input
STCP
Storage register clock pulse input
SHCPEN Shift register clock pulse enable input
SHLD
Shift register load input (active Low)
SHRST
Shift register reset input (active Low)
S Serial data select input
OE Output enable input
Qs Serial data output
I/On Parallel data outputs
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.) High/
Low
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
50/33
150/40
PIN CONFIGURATION
LOGIC SYMBOL
LOAD VALUE
High/Low
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
3.0mA/24mA
I/O0 1
I/O1 2
I/O2 3
I/O3 4
I/O4 5
I/O5 6
I/O6 7
I/O7 8
SHLD 9
GND 10
20 VCC
19 S
18 DS0
17 DS1
16 OE
15 STCP
14 SHCPEN
13 SHCP
12 SHRST
11 Qs
SF00375
18 17 1 2 3 4 5 6 7 8
Ds0 Ds1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
19 S
16 OE
15 STCP
14 SHCPEN
13 SHCP
12 SHRST
9 SHLD
Qs
VCC = Pin 20
GND = Pin 10
11
SF00376
1991 Oct 21
2 853–1583 04407









No Preview Available !

N74F598D Даташит, Описание, Даташиты
Philips Semiconductors
8-bit shift register with input storage registers (3-State)
Product specification
74F598
IEC/IEEE SYMBOL
16
SRG8
EN14
12
R
14
G4
13 4C5/4
9 C2
15
C1
19
G1
18
1, 5D
17
1, 5D
1
2D
Z6
3D
6, 14
2
2D
7, 14 3D Z7
3
4
5
6
7
8
2D
13, 14 3D Z13
11
SF00377
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
SHRST STCP SHCP SHLD S OE* I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
OPERATING MODE
L X L H X L L L L L L L L L L Clear shift register
L X L L XL
Invalid, state of shift register in-
determinate when signal is re-
moved
X X X X H I0 I1 I2 I3 I4 I5 I6 I7 O7 Load data to storage register
H X H L L Ds0 O0 O1 O2 O3 O4 O5 O6 O6 Shift right
H X H H L Ds1 O0 O1 O2 O3 O4 O5 O6 O6
H
L
L
XH
I0 I1
I2 I3
I4 I5 I6
I7
O7
Load data directly to shift regis-
ter
H
L
L
X
X
O0
O1
O2
O3
O4
O5
O6
O7
O7
Data transferred from storage
register to shift register
X X X X X H Z Z Z Z Z Z Z Z NC 3–State
H X H X X NC NC NC NC NC NC NC NC NC Hold
H
H
X
X
X
NC
NC
NC
NC
NC
NC
NC
NC
NC
Hold (no storage or shift register
load
Notes to function table
D0 – D7 = The level of the steady state inputs to the serial multiplexer.
H = High voltage level
I0 – I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip–flop while the flip–flop outputs ( except Q7) are isolated
from the I/O terminal.
L = Low voltage level
NC= No change
O0 – O7 = The level of the respective Qn flip–flop prior to the last clock Low–to–High transition
X = Don’t care
Z = High impedance ”off” state
* = When the OE input is High, all I/O terminals are at the High impedance state, sequential operation or cleaning of the register is not affected.
= Low–to–High clock transition
= Not Low–to–High clock transition
1991 Oct 21
3










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