N74F776N PDF даташит
Спецификация N74F776N изготовлена «Philips» и имеет функцию, называемую «Pi-bus transceiver». |
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Детали детали
Номер произв | N74F776N |
Описание | Pi-bus transceiver |
Производители | Philips |
логотип |
12 Pages
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INTEGRATED CIRCUITS
74F776
Pi-bus transceiver
Product specification
IC15 Data Handbook
Philips
Semiconductors
1990 Dec 19
No Preview Available ! |
Philips Semiconductors
Pi–bus transceiver
Product specification
74F776
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with equivalent load impedances
down to 10 ohms
• High drive (100mA) open collector drivers on B port
• Reduced voltage swing (1 volt) produces less noise and reduces
power consumption
• High speed operation enhances performance of backplane buses
and facilitates incident wave switching
• Compatible with Pi–bus and IEEE 896 Futurebus standards
• Built–in precision band–gap reference provides accurate receiver
thresholds and improved noise immunity
• Controlled output ramp and multiple GND pins minimize ground
bounce
• Glitch–free power up/power down operation
• Multiple package options
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F776 is an octal bidirectional latched transceiver and is
intended to provide the electrical interface to a high performance
wired–OR bus. The B port inverting drivers are low–capacitance open
collector with controlled ramp and are designed to sink 100mA from 2
volts. The B port inverting receivers have a 100 mV threshold region
and a 4ns glitch filter.
The 74F776 B port interfaces to ’Backplane Transceiver Logic’ (BTL).
BTL features a reduced (1V to 2V) voltage swing for lower power
consumption and a series diode on the drivers to reduce capacitive
loading. Incident wave switching is employed, therefore BTL
propagation delays are short. Although the voltage swing is less for
BTL, so is its receiver threshold, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and
crosstalk, low capacitive loading, superior noise margin and low
propagation delays. This results in a high bandwidth, reliable
backplane.
The 74F776 A port has TTL 3–state drivers and TTL receivers with a
latch function. A separate high–level control voltage input (VX) is
provided to limit the A side output level to a given voltage level (such
as 3.3V). For 5.0V systems, VX is simply tied to VCC.
The 74F776 has a designed feature to control the B output transitions
during power sequencing. There are two possible sequencing, They
are as follows:
1.When LE = low and OEBn = low then the B outputs are disabled until
the LE circuitry takes control. Then the B outputs will follow the A inputs,
making a maximum of one transition during power–up (or down).
2. If LE = high or OEBn = high then the B outputs will be disabled during
power–up (or down).
TYPE
74F776
TYPICAL PROPAGA-
TION DELAY
6.5ns
TYPICAL SUPPLY
CURRENT( TOTAL)
80mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C VCC = 5V ±10%, Tamb = –40°C to +85°C
PKG DWG #
28–pin plastic DIP (600 mil)
28–pin PLCC
N74F776N
N74F776A
I74F776N
I74F776A
SOT117-2
SOT261-2
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
A0 – A7
PNP latched inputs
B0 – B7
Data inputs with threshold circuitry
OEA
A output enable input (active high)
OEB0, OEB1
B output enable inputs (active low)
LE Latch enable input (active low)
A0 – A7
3–state outputs
B0 – B7
Open collector outputs
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
OC = Open collector.
74F (U.L.)
HIGH/LOW
3.5/0.117
5.0/0.167
1.0/0.033
1.0/0.033
1.0/0.033
150/40
OC/166.7
LOAD VALUE
HIGH/LOW
70µA/70µA
100µA/100µA
20µA/20µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
December 19, 1990
2
853 1121 01321
No Preview Available ! |
Philips Semiconductors
Pi–bus transceiver
Product specification
74F776
PIN CONFIGURATION
VCC 1
OEA 2
A0 3
GND 4
A1 5
A2 6
A3 7
GND 8
A4 9
A5 10
GND 11
A6 12
A7 13
VX 14
28 LE
27 B0
26 B1
25 GND
24 B2
23 B3
22 GND
21 B4
20 B5
19 B6
18 GND
17 B7
16 OEB1
15 OEB0
SF00422
IEC/IEEE SYMBOL
&
15
EN2
16
28
EN1
2 EN3
3 ID 2
3
5
6
7
9
10
12
13
27
26
24
23
21
20
19
17
SF00424
PIN CONFIGURATION PLCC
GND A0 OEA VCC LE B0 B1
4 3 2 1 28 27 26
A1 5
25 GND
A2 6
24 B2
A3 7
23 B3
GND 8
A4 9
PLCC
22 GND
21 B4
A5 10
20 B5
GND 11
19 B6
12 13 14 15 16 17 18
A6 A7 VXOEB0 OEB1 B7 GND
SF00423
LOGIC SYMBOL
3 5 6 7 9 10 12 13
A0 A1 A2 A3 A4 A5 A6 A7
15 OEB0
2 OEA
28 LE
16 OEB1
B0 B1 B2 B3 B4 B5 B6 B7
27 26 24 23 21 20 19 17
VCC = Pin 1, VX = Pin 14
GND = Pin 4, 8, 11, 18, 22, 25
SF00425
PIN DESCRIPTION
SYMBOL
PINS
A0 – A7
3, 5, 6, 7, 9, 10, 12, 13
B0 – B7 27, 26, 24, 23, 21, 20, 19, 17
OEB0
OEB1
OEA
LE
VX
15
16
2
28
14
TYPE
I/O
I/O
Input
Input
Input
Input
Input
NAME AND FUNCTION
PNP latched input/3–state output (with VX control option)
Data input with special threshold circuitry to reject noise/ open collector output, high
current drive
Enables the B outputs when both pins are low
Enables the A outputs when high
Latched when high (a special feature is built in for proper enabling times)
Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
December 19, 1990
3
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