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N74F843N PDF даташит

Спецификация N74F843N изготовлена ​​​​«Philips» и имеет функцию, называемую «Bus interface latches».

Детали детали

Номер произв N74F843N
Описание Bus interface latches
Производители Philips
логотип Philips логотип 

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N74F843N Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F841/842/843/845/846
Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
1999 Jun 23
Philips
Semiconductors









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N74F843N Даташит, Описание, Даташиты
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/
74F845/74F846
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
High impedance NPN base input structure minimizes bus loading
IIL is 20µA vs 1000A for AM29841 series
Buffered control inputs to reduce AC effects
Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
Positive and negative over-shoots are clamped to ground
3-State outputs glitch free during power-up and power-down
48mA sink current
Slim dual in-line 300 mil package
Broadside pinout
Pin-for-pin and function compatible with AMD AM29841-846
series
TYPE
74F841, 74F842
74F843, 74F845
74F846
TYPICAL
PROPAGATION
DELAY
5.5ns
5.5ns
6.2ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
60mA
75mA
60mA
DESCRIPTION
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE pins, the 74F843 has a Master Reset
(MR) pin and Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When MR is Low, the
outputs are Low if OE is Low. When MR is High, data can be
entered into the latch. When PRE is Low, the outputs are High, if OE
is Low, PRE overrides MR.
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE, MR and PRE pins, the 74F845 has two
addtitional OE pins making a total of three Output Enables (OE0,
OE1, OE2) pins.
The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user
control of the interface, e.g., CS, DMA, and RD/WR.
The 74F846 is the inverted output version of the 74F845.
ORDERING INFORMATION
PACKAGES
24-pin plastic Slim DIP (300 mil)
24-pin plastic SOL
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
N74F841N, N74F842N, N74F843N, N74F845N, N74F846N
N74F841D, N74F842D, N74F843D, N74F845D, N74F846D
PACKAGE DRAWING
NUMBER
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
Dn Data inputs
1.0/0.033
LE Latch Enable input
1.0/0.033
OE, OEn
Output Enable input (active Low)
1.0/0.033
MR Master Reset input (active Low)
1.0/0.033
PRE
Preset input (active Low)
1.0/0.033
Qn Data outputs
1200/80
Qn Data outputs
1200/80
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
24mA/48mA
24mA/48mA
1999 Jun 23
2 853–1208 21851









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N74F843N Даташит, Описание, Даташиты
Philips Semiconductors
Bus interface latches
PIN CONFIGURATION for 74F841
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
SF01279
LOGIC SYMBOL for 74F841
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13 LE
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
VCC = Pin 24
GND = Pin 12
23 22 21 20 19 18 17 16 15 14
SF01280
LOGIC SYMBOL (IEEE/IEC) for 74F841
1
EN
13
C1
2
1D
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
SF01281
Product specification
74F841/74F842/74F843/
74F845/74F846
PIN CONFIGURATION for 74F842
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
SF01282
LOGIC SYMBOL for 74F842
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13 LE
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
VCC = Pin 24
GND = Pin 12
23 22 21 20 19 18 17 16 15 14
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
EN
13
C1
2
1D
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
SF01284
1999 Jun 23
3










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