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PDF NB90234 Data sheet ( Hoja de datos )
| Número de pieza | NB90234 | |
| Descripción | 16-bit Proprietary Microcontroller | |
| Fabricantes | Fujitsu Media Devices Limited | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NB90234 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
s DESCRIPTION
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video
devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16F. The instruction
set for the F2MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT
architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high
speed.
The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous
transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit precision) × 8
channels, the D/A converter (8-bit precision) × 2 channels, the level comparator × 1 channel, the external interrupt
input × 4 lines, the 8-bit PPG timer (PWM/single-shot function) × 1 channel, the 8-bit PWM controller × 6 channels,
the 16-bit free run timer × 1 channel, the input capture unit × 4 channels, the output compare unit × 6 channels,
and the serial E2PROM interface.
*: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
F2MC-16F CPU block
• Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
• Instruction set optimized for controllers
Various data types supported (bit, byte, word, and long-word)
Extended addressing modes: 23 types
High coding efficiency
Higher-precision operation enhanced by a 32-bit accumulator
Signed multiplication and division instructions
(Continued)
s PACKAGE
100-pin Plastic LQFP
100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
1 page  
MB90230 Series
s PIN DESCRIPTION
Pin no.
80
81
82
83 to 90
Pin name
X0
X1
VCC
P00 to P07
D00 to D07
91 to 98 P10 to P17
D08 to D15
99, 100 P20 to P27
1 to 6
A00 to A07
7, 8 P30, P31
A08, A09
9
10 to 15
VSS
P32 to P37
A10 to A15
Circuit
type
A Oscillator pins
Function
— Power supply pin
G General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins serve as D00 to D07 pins in bus modes other than the
single-chip mode.
I/O pins for the lower eight bits of the external data bus.
These pins are enabled in an external-bus enabled mode.
G General-purpose I/O port
An input pull-up resistor can be added to the port by setting the pull-up
resistor setting register.
These pins are enabled in the single-chip mode with the external-bus
enabled and the 8-bit data bus specified.
I/O pins for the upper eight bits of the external data bus
These pins are enabled in an external-bus enabled mode with the 16-
bit data bus specified.
G General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins are enabled in the single-chip mode.
I/O pins for the lower eight bits of the external data bus
These pins are enabled in an external-bus enabled mode.
E General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
— Power supply pin
E General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
(Continued)
5
5 Page 
MB90230 Series
(Continued)
Pin no.
70
Pin name
P50
CLK
71 P51
RDY
72 P52
HAK
73 P53
HRQ
74 P54
WRH
75 RST
76 P55
WRL
77 P56
RD
78 P57
79 VSS
Circuit
type
Function
H This pin is enabled in the single-chip mode and when the CLK output
is disabled.
CLK output pin
This pin is enabled in an external-bus enabled mode with the CLK
output enabled.
F General-purpose I/O port
This port is enabled in the single-chip mode.
Ready signal input pin
This pin is enabled in an external-bus enabled mode.
E General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
E General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
E General-purpose I/O port
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled.
Write strobe output pin for the upper eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
B Reset signal input pin
E This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled
Write strobe output pin for the lower eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
The pin is a general-purpose I/O port.
E This pin is enabled in the single-chip mode.
Read strobe output pin for the data bus
This pin is enabled in an external-bus enabled mode.
E General-purpose I/O port
— Power pin (GND)
*1: Enabled in any standby mode
*2: Enabled only in the hardware standby mode
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet NB90234.PDF ] | |
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