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PDF NC7SZ125M5 Data sheet ( Hoja de datos )
| Número de pieza | NC7SZ125M5 | |
| Descripción | UHS Buffer | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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January 2014
NC7SZ125
TinyLogic® UHS Buffer with Three-State Output
Features
Ultra-High Speed: tPD 2.6 ns (Typical) into 50 pF
at 5 V VCC
High Output Drive: ±24 mA at 3 V VCC
Broad VCC Operating Range: 1.65 V to 5.5 V
Matches Performance of LCX Operated at
3.3 V VCC
Power Down High-Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5 V to 3 V
Translation
Proprietary Noise/EMI Reduction Circuitry
Ultra-Small MicroPak™ Packages
Space-Saving SOT23 and SC70 Packages
Description
The NC7SZ125 is a single buffer with three-state
output from Fairchild's Ultra-High Speed (UHS) of
TinyLogic®. The device is fabricated with advanced
CMOS technology to achieve ultra high speed with
high output drive while maintaining low static power
dissipation over a very broad VCC operating range. The
device is specified to operate over the 1.65 V to 5.5 V
range. The inputs and output are high impedance
above ground when VCC is 0 V. Inputs tolerate voltages
up to 6 V independent of VCC operating voltage. The
output tolerates voltages above VCC when in the 3-
STATE condition.
Ordering Information
Part Number Top Mark
Package
NC7SZ125M5X
7Z25
5-Lead SOT23, JEDEC MO-178 1.6 mm
NC7SZ125P5X
Z25 5-Lead SC70, EIAJ SC-88a, 1.25 mm Wide
NC7SZ125L6X
DD 6-Lead MicroPak™, 1.00 mm Wide
NC7SZ125FHX
DD 6-Lead, MicroPak2, 1x1 mm Body, .35mm Pitch
Packing Method
3000 Units on
Tape & Reel
3000 Units on
Tape & Reel
5000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 1996 Fairchild Semiconductor Corporation
NC7SZ125 • Rev. 1.0.5
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
VCC
Conditions
TA=+25°C
TA=-40 to +85°C Units Figure
Min. Typ. Max. Min. Max.
1.65
2.0 6.4 13.2 2.0
13.8
tPLH,tPHL Propagation Delay
1.80
2.50 ±0.20
3.30 ±0.30
5.00 ±0.50
CL=15 pF,
RD=1 M
S1=OPEN
2.0 5.3 11.0
0.8 3.4 7.5
0.5 2.5 5.2
0.5 2.1 4.5
2.0
0.8
0.5
0.5
11.5
8.0
5.5
4.8
ns
Figure 4
Figure 6
3.30 ±0.30 CL=50 pF,
5.00 ±0.50
RD=500
S1=OPEN
1.5 3.2 5.7
0.8 2.6 5.0
1.65 CL=50 pF,
2.0 8.4 15.0
1.80
RD=500
2.0 7.0 12.5
tPZL,tPZH Output Enable Time
2.50 ±0.20 RU=500
3.30 ±0.30
S1=GND for tPZH
S1=VIN for tPZL
1.5
1.5
4.6
3.5
8.5
6.2
5.00 ±0.50 VIN=2•VCC
0.8 2.8 5.5
1.65 CL=50 pF,
2.0 6.5 13.2
1.80
RD=500
2.0 5.4 11.0
tPLZ,tPHZ Output Disable Time
2.50 ±0.20 RU=500
3.30 ±0.30
S1=GND for tPHZ
S1=VIN for tPLZ
1.5
1.0
3.5
2.8
8.0
5.7
5.00 ±0.50 VIN=2•VCC
0.5 2.1 4.7
CIN Input Capacitance
0.00
4
COUT Output Capacitance
0.00
8
CPD
Power Dissipation
Capacitance(2)
3.30
5.00
17
24
1.5
0.8
2.0
2.0
1.5
1.5
0.8
2.0
2.0
1.5
1.0
0.5
6.0
5.3
15.6
13.0
9.0
6.5
5.8
14.5
ns
Figure 4
Figure 6
12.0
8.5
6.0
5.0
pF
pF Figure 5
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output lading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
Note:
3. CL includes load and stray capacitance.
Input PRR=1.0 MHz, tW=500 ns.
Figure 4. AC Test Circuit
Note:
4. Input=AC Waveform; tr=tf=1.8 ns;
PRR=10 MHz; Duty Cycle=50%.
Figure 5. ICCD Test Circuit
© 1996 Fairchild Semiconductor Corporation
NC7SZ125 • Rev. 1.0.5
Figure 6. AC Waveforms
www.fairchildsemi.com
5
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| PDF Descargar | [ Datasheet NC7SZ125M5.PDF ] | |
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