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PDF NCP1203 Data sheet ( Hoja de datos )
| Número de pieza | NCP1203 | |
| Descripción | PWM Current-Mode Controller | |
| Fabricantes | ON | |
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NCP1203
PWM Current-Mode
Controller for Universal
Off-Line Supplies Featuring
Standby and Short Circuit
Protection
Housed in SOIC−8 or PDIP−8 package, the NCP1203 represents a
major leap toward ultra−compact Switchmode Power Supplies and
represents an excellent candidate to replace the UC384X devices. Due
to its proprietary SMARTMOS™ Very High Voltage Technology, the
circuit allows the implementation of complete off−line AC−DC
adapters, battery charger and a high−power SMPS with few external
components.
With an internal structure operating at a fixed 40 kHz, 60 kHz or
100 kHz switching frequency, the controller features a high−voltage
startup FET which ensures a clean and loss−less startup sequence. Its
current−mode control naturally provides good audio−susceptibility
and inherent pulse−by−pulse control.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides improved efficiency at light loads
while offering excellent performance in standby conditions. Because
this occurs at a user adjustable low peak current, no acoustic noise
takes place.
The NCP1203 also includes an efficient protective circuitry which,
in presence of an output over load condition, disables the output
pulses while the device enters a safe burst mode, trying to restart.
Once the default has gone, the device auto−recovers. Finally, a
temperature shutdown with hysteresis helps building safe and robust
power supplies.
Features
• High−Voltage Startup Current Source
• Auto−Recovery Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• Current−Mode with Adjustable Skip−Cycle Capability
• Internal Leading Edge Blanking
• 250 mA Peak Current Capability
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
• Direct Optocoupler Connection
• Undervoltage Lockout at 7.8 V Typical
• SPICE Models Available for TRANsient and AC Analysis
• Pin to Pin Compatible with NCP1200
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
www.onsemi.com
MARKING
DIAGRAM
8
1
SOIC−8
D1, D2 SUFFIX
CASE 751
8
203Dx
ALYW
G
1
x = 4, 6, or 1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
8
1
PDIP−8
N SUFFIX
CASE 626
8
1203Pxx
AWL
YYWWG
1
xx = 40, 60, or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
PIN CONNECTIONS
Adj 1
FB 2
CS 3
GND 4
8 HV
7 NC
6 VCC
5 Drv
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 12
1
Publication Order Number:
NCP1203/D
1 page  
NCP1203
14.0
13.8
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
−50
−25 0 25 50 75 100
TEMPERATURE (°C)
Figure 3. VCC(on) Threshold versus
Temperature
125
8.4
8.2
8.0
7.8
7.6
7.4
7.2
−50
−25
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 4. VCC(min) Level versus Temperature
900
860
820
780
740
700
660
620
580
540
500
−50
−25
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 5. IC Current Consumption (No Load)
versus Temperature
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−50
−25
100 kHz
60 kHz
40 kHz
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 6. ICC Consumption (Loaded by 1 nF)
versus Temperature
8.0
7.5
7.0 60 kHz
6.5
40 kHz
6.0
5.5
5.0
4.5
4.0
−50
−25
100 kHz
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 7. HV Current Source at VCC = 10 V
versus Temperature
400
350
300
250
200
150
−50
−25 0
25 50 75 100
TEMPERATURE (°C)
Figure 8. IC Consumption at VCC = 6 V
versus Temperature
125
www.onsemi.com
5
5 Page 
ON/OFF
NCP1203
Q1
1
2
3
4
8
7
6
5
Figure 19. Another Way of Shutting Down the IC without a Definitive Latch−Off State
Full Latching Shutdown
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (overtemperature or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the VCC level exceeds the zener breakdown voltage,
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user unplugs the power supply.
OVP
Rhold
12 k
10 k
0.1 mF
10 k
NCP1203
18
27
36
45
CVCC LAux
Figure 20. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to let
the VCC ramp up (12.8 V) and down (4.9 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between VCC and GND. If the current sense
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user un−plugs the power supply, the controller is
still fed by its VCC capacitor and keeps activating the
MOSFET ON and OFF with a peak current limited by
Rsense. Unfortunately, if the quality coefficient Q of the
resonating network formed by Lp and Cbulk is low (e.g. the
MOSFET Rdson + Rsense are small), conditions are met to
make the circuit resonate and thus negatively bias the
controller. Since we are talking about ms pulses, the amount
of injected charge (Q = I x t) immediately latches the
controller which brutally discharges its VCC capacitor. If this
VCC capacitor is of sufficient value, its stored energy
damages the controller. Figure 21 depicts a typical negative
shot occurring on the HV pin where the brutal VCC discharge
testifies for latchup.
www.onsemi.com
11
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| PDF Descargar | [ Datasheet NCP1203.PDF ] | |
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