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PDF NCP1232 Data sheet ( Hoja de datos )
| Número de pieza | NCP1232 | |
| Descripción | Microprocessor Monitor | |
| Fabricantes | ON | |
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NCP1232
Microprocessor Monitor
The NCP1232 is a fully–integrated processor supervisor. It provides
three important functions to safeguard processor functionality:
precision power on/off reset control, watchdog timer and external
reset override.
On power–up, the NCP1232 holds the processor in the reset state for
a minimum of 250 msec after VCC is within tolerance to ensure a
stable system start–up.
Microprocessor functionality is monitored by the on–board
watchdog circuit. The microprocessor must provide a periodic
low–going signal on the ST input. Should the processor fail to supply
this signal within the selected time–out period (150 msec, 600 msec or
1200 msec), an out–of–control processor is indicated and the
NCP1232 issues a processor reset as a result.
The outputs of the NCP1232 are immediately driven active when
the PB input is brought low by an external push–button switch or other
electronic signal. When connected to a push–button switch, the
NCP1232 provides contact debounce.
The NCP1232 is packaged in a space–saving 8–pin plastic SOIC
package and requires no external components.
Features
• Precision Voltage Monitor
(Adjustable +4.5 V or +4.75 V)
• Reset Pulse Width (250 msec Min)
• No External Components
• Adjustable Watchdog Timer
(150 msec, 600 msec or 1.2 sec)
• Debounced Manual Reset Input for External Override
Applications
• Computers
• Controllers
• Intelligent Instruments
• Automotive Systems
• Critical µP Power Monitoring
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
NCP
1232
YWWXZ
1
YY, Y
WW
X
Z
= Year
= Work Week
= Assembly ID Code
= Subcontractor ID Code
PIN CONNECTIONS
8–Pin SOIC
PB RST 1
TD 2
TOL 3
GND 4
8 VCC
7 ST
6 RST
5 RST
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCP1232DR2
SO–8 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 0
1
Publication Order Number:
NCP1232/D
1 page  
NCP1232
tPB
PB RST
tPBD
RST
RST
VIL
VIH
tRST
Figure 3. Push–button Reset. The debounced PB RST
input ignores input pulses less than 1 msec and is
guaranteed to recognized pulses of 20 msec or greater
PUSH–BUTTON RESET
tST
ST
tTD
Figure 4. Strobe Input
NOTE: tTD is the maximum elapsed time between ST high–to–low
transistions (ST is activated by falling edges only) which will
keep the watchdog timer from forcing the reset outputs active
for a time of tRST. tTD is a function of the voltage at the TD pin,
as tabulated below.
CONDITION
tTD
MIN TYP MAX
TD PIN = 0 V
TD PIN = OPEN
TD PIN = VCC
62.5 msec
250 msec
500 msec
150 msec
600 msec
1200 msec
250 msec
1000 msec
2000 msec
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet NCP1232.PDF ] | |
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