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PDF NDB6030PL Data sheet ( Hoja de datos )
| Número de pieza | NDB6030PL | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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June 1997
NDP6030PL / NDB6030PL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as DC/DC converters and high efficiency
switching circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
Features
-30
A,
-30
V.
RDS(ON)
RDS(ON)
=
=
0.042
0.025
Ω
Ω
@
@
VGS= -4.5 V
VGS= -10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low RDS(ON).
175°C maximum junction temperature rating.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings
Symbol Parameter
TC = 25°C unless otherwise noted
NDP6030PL
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
PD Total Power Dissipation @ TC = 25°C
Derate above 25°C
TJ,TSTG
TL
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJC Thermal Resistance, Junction-to-Case
RθJA Thermal Resistance, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
-30
±16
-30
-90
75
0.5
-65 to 175
275
NDB6030PL
-65 to 175
2
62.5
Units
V
V
A
W
°C
°C
°C
°C/W
°C/W
NDP6030PL Rev.B1
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet NDB6030PL.PDF ] | |
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