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PDF NDC631N Data sheet ( Hoja de datos )

Número de pieza NDC631N
Descripción N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes Fairchild 
Logotipo Fairchild Logotipo



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NDC631N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
July 1996
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications in
notebook computers, portable phones, PCMICA cards, and
other battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline surface
mount package.
Features
4.1 A, 20 V. RDS(ON) = 0.06 @ VGS = 4.5 V
RDS(ON) = 0.075 @ VGS =2.7 V.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise note
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
43
52
61
NDC631N
20
8
4.1
15
1.6
1
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC631N Rev.D1

1 page




NDC631N pdf
Typical Electrical Characteristics (continued)
1.12
ID = 250µA
1.08
1.04
1
0.96
0.92
-50
-25 0
25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
10
5
VGS =0V
1
TJ = 125°C
0.1
25°C
0.01 -55°C
0.001
0.0001
0
0.2 0.4 0.6 0.8
1
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
1500
1000
600
300
200
f = 1 MHz
100 VGS = 0V
Ciss
Coss
Crss
50
0.1
0.2
0.5 1
2
5 10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Capacitance Characteristics.
20
5
ID = 4.1A
4
VDS = 5V
10V
15V
3
2
1
0
0 3 6 9 12
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
VIN
VGS
RGEN
G
VDD
RL
D
VOUT
DUT
S
Figure 11. Switching Test Circuit.
t d(on)
t on
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
INVERTED
50%
PULSE WIDTH
Figure 12. Switching Waveforms.
NDC631N Rev.D1

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