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PDF NDP4050 Data sheet ( Hoja de datos )
| Número de pieza | NDP4050 | |
| Descripción | N-Channel Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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July 1996
NDP4050 / NDB4050
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process has been especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are
needed.
15A, 50V. RDS(ON) = 0.10Ω @ VGS=10V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low RDS(ON).
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
____________________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
TC = 25°C unless otherwise noted
NDP4050
VDSS Drain-Source Voltage
VDGR
Drain-Gate Voltage (RGS < 1 MΩ)
VGSS Gate-Source Voltage - Continuous
- Nonrepetitive (tP < 50 µs)
ID Drain Current - Continuous
- Pulsed
PD Total Power Dissipation
Derate above 25°C
TJ,TSTG
TL
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
50
50
± 20
± 40
± 15
± 45
50
0.33
-65 to 175
275
NDB4050
Units
V
V
V
A
W
W/°C
°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP4050 Rev. B
1 page  
Typical Electrical Characteristics (continued)
1.15
1.1
ID = 250µA
1.05
1
0.95
0.9
-50
-25
0 25 50 75 100 125 150 175
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
20
VGS = 0V
10
5
TJ = 125°C
2
1
0.5
25°C
-55°C
0.2
0.1
0.4
0.6 0.8 1 1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
700
500
300
200
100
50
30
1
C iss
C oss
f = 1 MHz
VGS = 0V
C rss
23
5
10 20 30
V DS , DRAIN TO SOURCE VOLTAGE (V)
60
Figure 9. Capacitance Characteristics.
20
ID = 15A
15
10
VDS = 12V
24V
48V
5
0
0 5 10 15
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
20
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
Figure 11. Switching Test Circuit.
t d(on)
t on
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
INVERTED
50%
PULSE WIDTH
Figure 12. Switching Waveforms.
NDP4050 Rev. B
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NDP4050.PDF ] | |
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