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PDF NDP7051L Data sheet ( Hoja de datos )
| Número de pieza | NDP7051L | |
| Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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September 1996
NDP7051L / NDB7051L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
67 A, 50 V. RDS(ON) = 0.0145 Ω @ VGS= 5 V
RDS(ON) = 0.0115 Ω @ VGS= 10 V.
Low drive requirements allowing operation directly from logic
drivers. VGS(TH) < 2.0V.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low RDS(ON).
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
TC = 25°C unless otherwise noted
NDP7051L
VDSS Drain-Source Voltage
VDGR
Drain-Gate Voltage (RGS < 1 MΩ)
VGSS Gate-Source Voltage - Continuous
- Nonrepetitive (tP < 50 µs)
ID Drain Current - Continuous
- Pulsed
PD Maximum Power Dissipation @ TC = 25°C
Derate above 25°C
TJ,TSTG Operating and Storage Temperature Range
50
50
±16
±25
67
200
130
0.87
-65 to 175
NDB7051L
Units
V
V
V
A
W
W/°C
°C
© 1997 Fairchild Semiconductor Corporation
NDP7051L Rev.D/NDB7051L Rev.E
1 page  
Typical Electrical Characteristics (continued)
1.15
1.1
ID = 250µA
1.05
1
0.95
0.9
-50
-25
0 25 50 75 100 125 150 175
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage
Variation with Temperature.
60
2 0 VGS =0V
10
TJ = 125°C
1
0.5
0.1
0.01
25°C
-55°C
0.001
0.0001
0
0.2 0.4 0.6 0.8
1
V , BODY DIODE FORWARD VOLTAGE (V)
SD
1.2
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
6000
4000
3000
2000
1000
Ciss
Coss
500 f = 1 MHz
VGS = 0V
Crss
200
1
5 10 15 20
V , DRAIN TO SOURCE VOLTAGE (V)
DS
30
50
Figure 9. Capacitance Characteristics.
10
ID = 67A
8
6
VDS = 12V
24V
48V
4
2
0
0 20 40 60 80 100 120
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
VIN
VGEN
RGEN
G
RGS
VDD
RL
D
VOUT
DUT
S
Figure 11. Switching Test Circuit.
t d(on)
t on
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
INVERTED
50%
PULSE WIDTH
Figure 12. Switching Waveforms.
NDP7051L Rev.D/NDB7051L Rev.E
5 Page 
TO-263AB/D2PAK Tape and Reel Data and Package Dimensions, continued
TO-263AB/D2PAK (FS PKG Code 45)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 1.4378
August 1998, Rev. A
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NDP7051L.PDF ] | |
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