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PDF NDS332P Data sheet ( Hoja de datos )
| Número de pieza | NDS332P | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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June 1997
NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
-1 A, -20 V, RDS(ON) = 0.41 Ω @ VGS= -2.7 V
RDS(ON) = 0.3 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
________________________________________________________________________________
D
AEsolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
GS
NDS332P
-20
±8
-1
-10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS332P Rev. E
1 page  
Typical Electrical Characteristics (continued)
1.12
I D = -250µA
1.08
1.04
1
0.96
0.92
-50
-25
0
25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
1
VGS =0V
0.1
0.05
0.01
0.001
TJ = 125°C
25°C
-55°C
0.0001
0
0.2 0.4 0.6 0.8
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1
Figure 8. Body Diode ForwardVoltageVariation with
Source Current and Temperature.
500
300
200 Ciss
100 Coss
50
f = 1 MHz
30 VGS = 0V
Crss
20
0.1
0.2
0.5 1
2
5 10
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
20
Figure 9. Capacitance Characteristics.
5
ID = -1A
4
3
2
1
0
01
VDS = -5V
-15V
-10V
23
Q g , GATE CHARGE (nC)
4
5
Figure 10. Gate Charge Characteristics.
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS332PRev. E
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet NDS332P.PDF ] | |
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