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PDF NDS352AP Data sheet ( Hoja de datos )
| Número de pieza | NDS352AP | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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February 1997
NDS352AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage applications
such as notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are needed in a
very small outline surface mount package.
Features
-0.9 A, -30 V. RDS(ON) = 0.5 Ω @ VGS = -4.5 V
RDS(ON) = 0.3 Ω @ VGS = -10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
GS
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS352AP
-30
±20
±0.9
±10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS352AP Rev.D
1 page  
Typical Electrical Characteristics (continued)
1.1
1.08
1.06
ID = - 2 5 0 µ A
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
4
VGS = 0V
1
0.1
0.01
TJ = 125°C
25°C
-55°C
0.001
0.0001
0
0.2 0.4 0.6 0.8 1 1.2
-V SD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
400
300
200
Ciss
Coss
100
50
30
20
0 .1
f = 1 MHz
VGS = 0 V
Crss
0 .2
0 .5 1
2
5 10
-VDS , DRAIN TO SOURCE VOLTAGE (V)
20 30
Figure 9. Capacitance Characteristics.
10
ID = -0.9A
8
VDS= -5V -10
-15
6
4
2
0
01234
Q , GATE CHARGE (nC)
g
Figure 10. Gate Charge Characteristics.
5
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS352Ap Rev.C
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NDS352AP.PDF ] | |
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