NDS352P PDF даташит
Спецификация NDS352P изготовлена «Fairchild» и имеет функцию, называемую «P-Channel Logic Level Enhancement Mode Field Effect Transistor». |
|
Детали детали
Номер произв | NDS352P |
Описание | P-Channel Logic Level Enhancement Mode Field Effect Transistor |
Производители | Fairchild |
логотип |
6 Pages
No Preview Available ! |
March 1996
NDS352P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-0.85A, -20V. RDS(ON) = 0.5Ω @ VGS = -4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
____________________________________________________________________________________________
D
GS
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
NDS352P
-20
±12
±0.85
±10
0.5
0.46
-55 to 150
250
75
© 1997 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
NDS352P Rev. F1
No Preview Available ! |
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
IDSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
IGSSF
Gate - Body Leakage, Forward
IGSSR
Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note 2)
VGS = 0 V, ID = -250 µA
VDS = -16 V, VGS = 0 V
VGS = 12 V, VDS = 0 V
VGS = -12 V, VDS = 0 V
-20
TJ =125°C
-5
-20
100
-100
V
µA
µA
nA
nA
VGS(th)
RDS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
ID(ON)
On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = -250 µA
-0.8 -1.6 -2.5
TJ =125°C -0.5 -1.3 -2.2
VGS = -4.5 V, ID = -0.85 A
0.46 0.5
TJ =125°C
0.59 0.7
VGS = -10 V, ID = -1 A
0.35
VGS = -4.5 V, VDS = -5 V
-2
VDS = -5 V, ID = -0.85 A
1.5
V
Ω
A
S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
125 pF
140 pF
45 pF
td(on) Turn - On Delay Time
tr Turn - On Rise Time
td(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VDD = -10 V, ID = -1 A,
VGS = -10 V, RGEN = 50 Ω
VDS = -10 V, ID = -0.85 A,
VGS = -5 V
8 15 ns
19 30 ns
64 90 ns
61 90 ns
2.2 4 nC
1 nC
2 nC
NDS352P Rev. F1
No Preview Available ! |
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter
Conditions
Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS Maximum Continuous Drain-Source Diode Forward Current
-0.6 A
ISM Maximum Pulsed Drain-Source Diode Forward Current
-5 A
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -0.85 A (Note 2)
-0.92 -1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
( ) = = = ( ) ×PD t
TJ −TA
RθJ A(t)
TJ −TA
RθJ C+RθCA(t)
I
2
D
t
RDS(ON ) TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper.
1 a 1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS352P Rev. F1
Скачать PDF:
[ NDS352P.PDF Даташит ]
Номер в каталоге | Описание | Производители |
NDS352AP | P-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
NDS352P | P-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |