NDS355N PDF даташит
Спецификация NDS355N изготовлена «Fairchild» и имеет функцию, называемую «N-Channel Logic Level Enhancement Mode Field Effect Transistor». |
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Детали детали
Номер произв | NDS355N |
Описание | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
Производители | Fairchild |
логотип |
6 Pages
No Preview Available ! |
March 1996
NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.6A, 30V. RDS(ON) = 0.125Ω @ VGS = 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
GS
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to -Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS355N
30
20
± 1.6
± 10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS355N Rev. D1
No Preview Available ! |
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter
Conditions
OFF CHARACTERISTICS
BVDSS
IDSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
VGS = 0 V, ID = 250 µA
VDS = 24 V, VGS = 0 V
IGSSF Gate - Body Leakage, Forward
IGSSR Gate - Body Leakage, Reverse
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VGS = 12 V, VDS = 0 V
VGS = -12 V, VDS= 0 V
VDS = VGS, ID = 250 µA
RDS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 1.6 A
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
tD(on) Turn - On Delay Time
tr Turn - On Rise Time
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
VGS = 10 V, ID = 1.9 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID = 1.6 A
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
VDD = 10 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω
VDS = 10 V, ID = 1.6 A,
VGS = 5 V
Min Typ Max Units
30
TJ=125°C
V
1 µA
10 µA
100 nA
-100 nA
1 1.6 2
V
TJ=125°C 0.5 1.3 1.5
0.125 Ω
TJ=125°C
0.25
0.085
6A
3.5 S
245 pF
130 pF
20 pF
15 30 ns
14 30 ns
12 25 ns
4 10 ns
3.5 5 nC
1 nC
2 nC
NDS355N Rev. D1
No Preview Available ! |
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter
Conditions
Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS Maximum Continuous Source Current
0.6 A
ISM Maximum Pulse Source Current (Note 2)
6A
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.6 A
0.8 1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
( ) = = = ( ) ×PD t
TJ −TA
RθJ A(t)
TJ −TA
RθJ C+RθCA(t)
I
2
D
t
RDS(ON ) TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper.
1 a 1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS355N Rev. D1
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Номер в каталоге | Описание | Производители |
NDS355AN | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
NDS355N | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild |
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