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PDF NDS9952A Data sheet ( Hoja de datos )
| Número de pieza | NDS9952A | |
| Descripción | Dual N & P-Channel Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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February 1996
NDS9952A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P-channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
Features
N-Channel 3.7A, 30V, RDS(ON)=0.08Ω @ VGS=10V.
P-Channel -2.9A, -30V, RDS(ON)=0.13Ω @ VGS=-10V.
High density cell design or extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
________________________________________________________________________________
54
63
72
81
Absolute Maximum Ratings
Symbol Parameter
TA= 25°C unless otherwise noted
N-Channel
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
(Note 1a)
30
± 20
± 3.7
± 15
PD Power Dissipation for Dual Operation
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
2
1.6
1
0.9
-55 to 150
78
40
P-Channel
-30
± 20
± 2.9
± 10
Units
V
V
A
W
°C
°C/W
°C/W
NDS9952A.SAM
1 page  
Typical Electrical Characteristics: N-Channel (continued)
1.12
I D = 250µA
1.08
1.04
1
0.96
0.92
-50
-25
0
25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature.
10
5 V GS = 0V
1
0.5 TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.2
0.4 0.6 0.8 1 1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature.
1000
800
500
300
200
C iss
C oss
100 f = 1 MHz
V GS = 0V
C rss
50
0.1
0.2
0.5 1
2
5 10
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 9. N-Channel Capacitance Characteristics.
10
ID = 3.7A
8
6
VDS = 10V
20V
15V
4
2
0
0 2 4 6 8 10 12
Q g , GATE CHARGE (nC)
Figure 10. N-Channel Gate Charge Characteristics.
10
V DS=10V
8
6
TJ= -55°C
25°C
125°C
4
2
0
0 2 4 6 8 10
I D , DRAIN CURRENT (A)
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
NDS9952A.SAM
5 Page 
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
Tc
A0 P1 D1
User Direction of Feed
E1
F
E2
W
Dimensions are in millimeter
Pkg type
A0
SOIC(8lds) 6.50
(12mm)
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
SOIC(8lds) Reel Configuration: Figure 4.0
Typical
component
A0 center line
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7" Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13" Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7" Dia
12mm
13" Dia
Dimensions are in inches and millimeters
Dim A Dim B
Dim C
7.00
177.8
13.00
330
0.059
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
2.165
55
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NDS9952A.PDF ] | |
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