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NE5037 PDF даташит

Спецификация NE5037 изготовлена ​​​​«Philips» и имеет функцию, называемую «6-Bit A/D converter parallel outputs».

Детали детали

Номер произв NE5037
Описание 6-Bit A/D converter parallel outputs
Производители Philips
логотип Philips логотип 

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NE5037 Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
6-Bit A/D converter (parallel outputs)
Product specification
NE5037
DESCRIPTION
The NE5037 is a low cost, complete successive-approximation
analog-to-digital (A/D) converter, fabricated using Bipolar/I2L
technology. With an external reference voltage, the NE5037 will
accept input voltages between 0V and VREF. An external START
pulse of at least 300ns in duration will provide the 6-bit result of the
conversion in parallel format. Full conversion with no missing codes
occurs in 9µs.
FEATURES
TTL-compatible inputs and outputs
3-State output buffer
Easy interface to CMOS microprocessors
Fast conversion—9µs
Guaranteed no missing codes over full temp range
Single-supply operation, +5V
Positive true binary outputs
High-impedance analog inputs
APPLICATIONS
Temperature control
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Dual In-Line Package (DIP)
BLOCK DIAGRAM
PIN CONFIGURATION
N Package
VCC 1
VREF 2
VIN 3
ANALOG GND 4
DIGITAL GND 5
CLK 6
START 7
CS 8
µP-based appliances
Light level monitors
Head position sensing
Electronic toys
Joystick interface
TOP VIEW
16 B5 (MSB)
15 B4
14 B3
13 B2
12 B1
11 B0
10 EOC
9 EO
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
NE5037N
DWG #
0406C
VCC
1
VREF 2
VIN 3
AGND 4
5
DGND
6
CLK
IIN
V/I
1/2
LSB
6–BIT
DAC
IO
V/I
CONTROL
LOGIC
SAR
7
START
8
CS
9
EOC
COM
16
DB DB5
11
DB DBO
EOC 10 EOC
August 31, 1994
582 853-0939 13721









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NE5037 Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
6-Bit A/D converter (parallel outputs)
Product specification
NE5037
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VCC
VREF
VIN(Analog)
VIN(Digital)
DOUT
Power supply voltage
Reference voltage
Analog input voltage
Digital input voltage (CS, OE, START, CLK)
Data outputs (DB0 to DB5)
3-state mode
Enabled mode (each output)
EOC
End of conversion
GND
TA
TSTG
TSOLD
PD
Analog GND to digital GND
Operating temperature range
Storage temperature range
Lead soldering temperature (10 seconds)
Maximum power dissipation, TA=25°C (still-air)1
N package
NOTES:
1. Derate above 25°C at the following rates:
N package=11.6mW/°C
RATING
7
7
7
7
7
5
VCC
±1
0 to 70
-65 to 150
300
1450
UNIT
V
V
V
V
V
mA
V
°C
°C
°C
mW
DC ELECTRICAL CHARACTERISTICS
VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C TA 70°C unless otherwise specified. Typical values are specified at 25°C
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min Typ
Max
UNIT
Resolution
6 6 6 Bits
Relative accuracy1,2
1/4 1/2 LSB
VCC Positive supply voltage
+4.75 +5.0 +5.50
V
εFS Full-scale gain error2,3,4
εZS Zero-scale offset error2
VREF=2.0V, TA=25°C
VREF=2.0V, TA=25°C
±1 ±2
±1/2 -1/2, +2
LSB
LSB
PSR
Power supply rejection, Max change in full-scale2
VREF=2.0V, 4.75VVCC5.5V
±1/2 ±1
LSB
IIN Analog input bias current
0VIN2.5V
1 10 µA
IREF Reference bias current
0VREF2.5V
1 10 µA
RIN Analog input resistance
3 30
M
VIH Logic ”1’ input voltage
2.0 V
VIL Logic ”0’ input voltage
0.8 V
IIH Logic ”1’ input current
10 µA
IIL Logic ”0’ input current
1 10 µA
IOH Logic ”1’ output current5
IOL Logic ”0’ output current5
2.4VVOH
VOL0.4V
300
1.6
µA
mA
IOZ 3-State leakage current
±0.1 ±40
µA
ICC Positive supply current
18 24 mA
PD Power dissipation
132 mW
NOTES:
1. Relative accuracy is defined as the deviation of the code transition points from the ideal code transition points on a straight line drawn from
zero-scale to full-scale of the device.
2. Specifications given in LSBs refer to the weight of the least significant bit at the 6-bit level which is 1.56% of the full-scale voltage.
3. Full-scale gain error is the deviation of the full-scale code transition point (111110 to 111111) from its ideal value.
4. The analog input voltage (VIN) range is 0V to VREF nominally, with the output remaining at 111111 even though the input may increase from
VREF to VCC. (For optimum performance, VREF can be any value from 1.5V to 2.5V.)
5. The data outputs have active pull-ups. The EOC line is open-collector with a nominal 5kinternal pull-up resistor.
August 31, 1994
583









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NE5037 Даташит, Описание, Даташиты
Philips Semiconductors Linear Products
6-Bit A/D converter (parallel outputs)
Product specification
NE5037
AC ELECTRICAL CHARACTERISTICS
VCC=5.0V; VREF=2.0V; Clock=1MHz; 0°C TA 70°C unless otherwise specified. Typical values are specified at 25°C (Refer to AC test
figures.)
SYMBOL
PARAMETER
LIMITS
TO FROM TEST CONDITIONS
UNIT
Min Typ Max
fMAX
tW
Maximum clock frequency
Start pulse width
Minimum positive/negative
clock pulse width
1 MHz
300 ns
300 ns
tCONV
Conversion time
9 Clock cycles
tP (OUT DATA) Propagation delay1
Data out OE TA=25°C tR=tF20ns
500 ns
tP (OUT EOC) Propagation delay2
EOC
Clock TA=25°C tR=tF20ns
800 ns
tP (3-STATE) Propagation delay, 3-State
3-State Data OE
TA=25°C tR=tF20ns
500 ns
NOTES:
1. Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE.
2. Propagation delay of EOC is defined as the delay in EOC going low, following the low going edge of the 9th clock pulse after the start pulse.
CIRCUIT DESCRIPTION
The comparator determines whether the output current of the DAC
NE5037 is a complete 6-bit, parallel output, microprocessor
is greater or less than the input current, which is converted from the
compatible, A/D converter which incorporates the
unknown analog input voltage through the V/I converter. If the DAC
successive-approximation method. The chip includes the internal
output is greater, that bit of the DAC is set to ”0’ and the
control logic, the successive-approximation register (SAR), 6-bit
corresponding output buffer goes to ”0’ simultaneously. If it is less, it
DAC, comparator and output buffers. An externally-generated clock
stays at ‘1’ and the output buffer also stays at ‘1’. On successive
source (max frequency=1MHz) must be provided to Pin 6. An
clock pulses, successive bits of the DAC are tried and the
external reference voltage supplied to Pin 2 sets the full-scale range
corresponding output buffer represents the bits of the DAC. On the
of the A/D converter.
eighth low-going edge of the clock pulse (after the receipt of the start
pulse), the EOC pin goes low, thereby indicating that the conversion
The CS pin must be at a low level prior to the start of the conversion
is complete. The output data is now valid. In order to access the
process. Upon receipt of a START pulse, the internal control logic
result of the conversion, the OE pin must be set to a low level. EOC
resets the SAR. On the first low-going edge of the clock pulse,
is reset to a high state when OE is low. When OE is in a ”1’ state,
successive approximation conversion commences. Successive bits
beginning with the MSB (D5) are supplied to the input of the internal
6-bit current output DAC by the I2L successive approximation
ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉregister.
the output buffers are in a high impedance state.
Refer to Figure 1 for the timing diagram.
ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉCS
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉDON’TCARE
START
CLK
OE
EOC
DATA
OUTPUTS
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DATA
READY
HIGH
AVAILABLE
Figure 1. Timing Diagram
HIGH
AVAILABLE
August 31, 1994
584










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