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PDF NTP75N03R Data sheet ( Hoja de datos )
| Número de pieza | NTP75N03R | |
| Descripción | Power MOSFET 75 Amps / 25 Volts N-Channel D2PAK / TO-220 | |
| Fabricantes | ON Semiconductor | |
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NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
N−Channel D2PAK, TO−220
Features
• Planar HD3e Process for Fast Switching Performance
• Low RDS(on) to Minimize Conduction Loss
• Low Ciss to Minimize Driver Loss
• Low Gate Charge
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C
− Single Pulse (tp = 10 ms)
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
RqJC
PD
ID
IDM
RqJA
PD
ID
RqJA
PD
ID
TJ, Tstg
25
±20
1.68
74.4
Vdc
Vdc
°C/W
W
75 A
225 A
60 °C/W
2.08 W
12.6 A
100 °C/W
1.25
9.7
−55 to
150
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc, IL = 12 Apk,
L = 1 mH, RG = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
EAS 71.7 mJ
TL 260 °C
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
http://onsemi.com
75 AMPERES
25 VOLTS
RDS(on) = 5.6 mΩ (Typ)
4
4
12
3
1
2
3
TO−220AB
CASE 221A
STYLE 5
D2PAK
CASE 418AA
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
P75N03R
YWW
1
Gate
3
Source
1
Gate
75N03R
YWW
23
Drain Source
2
Drain
75N03
Y
WW
= Device Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTP75N03R
NTB75N03R
NTB75N03RT4
TO−220AB
D2PAK
D2PAK
50 Units/Rail
50 Units/Rail
800/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 2
1
Publication Order Number:
NTB75N03R/D
1 page  
NTB75N03R, NTP75N03R
8 1000
6
4
Q1
QT
Q2
VGS
2
ID = 35 A
TJ = 25°C
0
0 4 8 12 16
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
10
1
1
td(off)
td(on)
tf
tr
VDS = 10 V
ID = 35 A
VGS = 10 V
10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
70
VGS = 0 V
60
50
40
30
TJ = 150°C
20
10
TJ = 25°C
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NTP75N03R.PDF ] | |
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