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PDF NTQS6463 Data sheet ( Hoja de datos )
| Número de pieza | NTQS6463 | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTQS6463
Power MOSFET
−20 V, −6.8 A, P−Channel TSSOP−8
Features
• New Low Profile TSSOP−8 Package
• Ultra Low RDS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperatures
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless
Telephones
• Lithium Ion Battery Applications
• Note Book PC
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain Current (Note 1)
− Continuous @ TA = 25°C
− Continuous @ TA = 70°C
− Pulsed (Note 3)
Total Power Dissipation (Note 1)
@ TA = 25°C
Drain Current (Note 2)
− Continuous @ TA = 25°C
− Continuous @ TA = 70°C
− Pulsed (Note 3)
Total Power Dissipation (Note 2)
@ TA = 25°C
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 40 V, IL = 18.4 A,
L = 5.0 mH, RG = 25 W)
Thermal Resistance −
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
VDSS
VGS
ID
ID
IDM
PD
ID
ID
IDM
PD
TJ, Tstg
EAS
−20
"12
−5.5
−4.4
"30
0.93
−6.8
−5.4
"30
1.39
−55 to
+150
845
V
V
A
W
A
W
°C
mJ
RqJA
°C/W
134
90
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum 3″ X 3″ FR−4 board, steady state.
2. Mounted on 1″ square (1 oz.) board, steady state.
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
VDSS
−20 V
RDS(on) TYP
20 mW @ −10 V
ID MAX
−6.8 A
P−Channel
D
G
S
MARKING
DIAGRAM
8
TSSOP−8
463
CASE 948S
YWW
PLASTIC
N
1
463 = Device Code
Y = Year
WW = Work Week
N = MOSFET
PIN ASSIGNMENT
D1
S2
S3
G4
8D
7S
6S
5D
Top View
ORDERING INFORMATION
Device
Package
Shipping†
NTQS6463
TSSOP−8 100 Units/Rail
NTQS6463R2
TSSOP−8 3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 2
1
Publication Order Number:
NTQS6463/D
1 page  
NTQS6463
5
4
3
Q1
2
QT
VGS = −4.5
Q2
1000
VDD = −16 V
ID = −6.8 A
VGS = −4.5 V
100
td(off)
tf
tr
1 TJ = 25°C
ID = −6.8 A
0
0 4 8 12 16 20 24 28
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1.2
VGS = 0 V
TJ = 25°C
0.8
0.4
0
0.4
0.5
0.6
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
0.7
td(on)
10
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
10
Mounted on 2″ sq. FR4 board (1″ sq. 1 oz. Cu 0.06″ thick single sided)
10 ms
100 ms
1 ms
10 ms
1
VGS = −4.5 V
SINGLE PULSE
TC = 25°C
0.1
RDS(on) LIMIT
THERMAL LIMIT
0.01
0.1
PACKAGE LIMIT
1
10
dc
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr, tf) do not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature.
Maximum energy at currents below rated continuous ID can
safely be assumed to equal the values indicated.
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NTQS6463.PDF ] | |
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