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PDF OQ8868 Data sheet ( Hoja de datos )
| Número de pieza | OQ8868 | |
| Descripción | Digital Servo Integrated Circuit Silent DSICS | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
OQ8868
Digital Servo Integrated Circuit
Silent (DSICS)
Product specification
Supersedes data of 1996 Apr 11
File under Integrated Circuits, IC01
1997 Feb 12
1 page  
Philips Semiconductors
Digital Servo Integrated Circuit Silent
(DSICS)
Product specification
OQ8868
PINNING
SYMBOL
TEST1
VrefH
D1
D2
D3
VrefL
D4
S1
S2
VSSA
VDDA
XTLR
VSSD5
OTD
RSTI
SILD
SICL/SCL
SIDA/SDA
ENIIC
INTREQ
XTALI
XTALO
VSSD4
RAB
DA
CDIC
RSTO
CLKO
VSSD3
VDDD3
RA
FO
SL
VSSD2
RP
TL
FOK
FTC
VSSD1
VDDD1
1997 Feb 12
PIN DESCRIPTION
1 test input 1 (LOW for normal operation); internal pull-down
2 high reference for A/D converter (input)
3 unipolar current input (central diode signal input)
4 unipolar current input (central diode signal input)
5 unipolar current input (central diode signal input)
6 low reference for A/D converter (input)
7 unipolar current input (central diode signal input)
8 unipolar current input (central diode signal input)
9 unipolar current input (central diode signal input)
10 analog ground
11 analog supply voltage
12 reference current input
13 digital ground 5
14 off track detector (output)
15 reset input (active HIGH)
16 serial host interface load
17 serial host interface clock /I2C-bus clock (SCL)
18 serial host interface data /I2C-bus data (SDA)
19 enable I2C-bus serial format (active LOW)
20 interrupt request output (active LOW)
21 oscillator input
22 oscillator output
23 digital ground 4
24 serial decoder interface load (output)
25 serial decoder interface data (input/output)
26 serial decoder interface clock (output)
27 reset output (active LOW)
28 clock buffer output
29 digital ground 3
30 digital supply voltage 3
31 radial actuator output
32 focus actuator output
33 sledge output
34 digital ground 2
35 radial polarity signal
36 track loss signal
37 focus OK output
38 fast track counting input (internal pull-down)
39 digital ground
40 digital supply voltage 1
5
5 Page 
Philips Semiconductors
Digital Servo Integrated Circuit Silent
(DSICS)
Product specification
OQ8868
The communication is bi-directional and processes 8-bit
words (byte, MSB first). The data present on SIDA is
clocked with the positive edge of SICL. A single
information exchange consists of one command byte and
up to seven data bytes.
The first byte defines the command, and is always input to
the DSICS. This byte defines whether data has to be
written to or read from the DSICS. If data has to be written
to the DSICS, this byte also specifies the number of data
bytes. The number of bytes read from the DSICS can vary
from 0 to 128 and only depends on how many the
microcontroller wants to read.
Serial decoder interface
The DSICS is able to control the decoder (SAA7345)
through a second serial interface. If this connection is
made, high-level features such as auto start-up and
interrupt on subcode discontinuity can be used. In this
case, the microcontroller has to communicate through the
DSICS to the decoder.
The interface to the decoder is a 3-line serial bus
comprising the following signals:
• Clock line (CDIC)
• Data line (DA)
• Control line (RAB).
The serial bus is fully controlled by the DSICS, although it
can be disabled by the microcontroller.
These frequencies are derived from the currently popular
decoder IC frequencies. It is also possible to drive the
clock circuit with a TTL compatible external clock signal.
The clock buffer output (CLKO) can supply the system
clock or half the system clock (also switchable under
software control via the serial bus) to be used as clock
generator for other ICs. The oscillator circuit is optimized
for low power dissipation, thus for applications beyond 8×
the clock signal must be supplied external at pin XTALI.
Reset
Reset is controlled by means of the RSTI pin (active
HIGH). This circuit ensures correct initialization of the
digital circuit and the output stages. The minimum reset
time is 250 ns. The inverse synchronized reset signal is
available on the output pin RSTO. This signal can be used
to reset the decoder and disable the SZA1010 (digital
output stages) during a reset.
Laser drive on
The LDO pin is used to switch the laser drive off and on. It
is an open drain output. When the laser is on, the output
has a high impedance. This pin is automatically driven
when the focus control loop is switched on.
Clock generation
The DSICS should run internally with a clock of
8.4672 MHz. The circuit that generates the clock has three
modes: the oscillator frequency divided by 2, 3 or 4
(software controlled). Therefore, it is possible to connect a
crystal or a resonator with a frequency of 8.4672, 11.2896
or 16.9344 MHz. For the best performance, use of the
16.9344 MHz input frequency is recommended for
8× applications. For higher speeds the next clock
frequencies are recommended:
• 22.0147 MHz for 10 × CD-ROM data rate
(8 × clock frequency +30%)
• 25.4016 MHz for 12 × CD-ROM data rate
(8 × clock frequency +50%)
• 33.8688 MHz for 16 × CD-ROM data rate, including
DVD (8 × clock frequency +100%)
1997 Feb 12
11
11 Page | ||
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| PDF Descargar | [ Datasheet OQ8868.PDF ] | |
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