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OR3LP26B PDF даташит

Спецификация OR3LP26B изготовлена ​​​​«Agere Systems» и имеет функцию, называемую «Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface».

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Номер произв OR3LP26B
Описание Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
Производители Agere Systems
логотип Agere Systems логотип 

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OR3LP26B Даташит, Описание, Даташиты
Data Sheet
March 2000
ORCA® OR3LP26B Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design imple-
mentation, coupled with the high bandwidth of an
industry-standard PCI interface. The ORCA
OR3LP26B (a member of the Series 3+ FPSC family)
provides a full-featured 33/50/66 MHz, 32-/64-bit PCI
interface, fully designed and tested, in hardware, plus
FPGA logic for user-programmable functions.
PCI Bus Core Highlights
s Implemented in an ORCA Series 3 OR3L125B
base array, displacing the bottom ten rows of 28
columns.
s Core is a well-tested ASIC model.
s Fully compliant to Revision 2.2 of PCI Local Bus
specification.
s Operates at PCI bus speeds up to 66 MHz on a
32-/64-bit wide bus.
s Comprises two independent controllers for Master
and Target.
s Meets/exceeds all requirements for PICMG* Hot
Swap friendly silicon, full Hot Swap model, per the
CompactPCI* Hot Swap specification, PICMG 2.1
R1.0.
s PCI SIG Hot Plug (R1.0) compliant.
s Four internal FIFOs individually buffer both direc-
tions of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
s Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target
interface. The dual 64-bit data paths extend into
the FPGA logic, permitting full-bandwidth, simulta-
neous bidirectional data transfers of up to
528 Mbytes/s to be sustained indefinitely.
s Can be configured to provide either two 64-bit
buses (one in each direction) to be multiplexed
between Master and Target, or four independent
32-bit buses.
s Provides many hardware options in the PCI core
that are set during FPGA logic configuration.
s Operates within the requirements of the PCI 5 V
and 3.3 V signaling environments and 3.3 V com-
mercial environmental conditions, allowing the
same device to be used in 5 V or 3.3 V PCI sys-
tems.
s FPGA is reconfigurable via the PCI interface's con-
figuration space (as well as conventionally), allow-
ing the FPGA to be field-updated to meet late-
breaking requirements of emerging protocols.
* PICMG and CompactPCI are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic
Device
OR3LP26B
Usable Gates
Number of
LUTs
Number of
Registers
Max User
RAM
Max User
I/Os
60K—120K
4032
5304
64K
259
Array
Size
18 x 28
Number of
PFUs
504
† The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4
RAM (or 512 gates) per PFU.









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OR3LP26B Даташит, Описание, Даташиты
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Table of Contents
Contents
Page Contents
Page
Introduction ..........................................................................1
PCI Bus Core Highlights ......................................................1
Figures .................................................................................2
Tables ..................................................................................3
FPSC Highlights ...................................................................5
Software Support .................................................................6
Description ...........................................................................7
What Is an FPSC? ............................................................7
FPSC Overview .................................................................7
FPSC Gate Counting ........................................................7
FPGA/Embedded Core Interface ......................................7
ORCA Foundry Development System ..............................7
FPSC Design Kit ...............................................................8
FPGA Logic Overview .......................................................8
PLC Logic ..........................................................................8
PIC Logic ...........................................................................9
System Features ...............................................................9
Routing ..............................................................................9
Configuration .....................................................................9
Boundary Scan ..................................................................9
More Series 3 Information .................................................9
OR3LP26B Overview .........................................................10
Device Layout .................................................................10
PCI Local Bus .................................................................10
OR3LP26B PCI Bus Core Overview ...............................12
PCI Bus Interface ............................................................12
Embedded Core Options/FPGA Configuration ...............13
PCI Bus Core Detailed Description ....................................14
PCI Bus Commands ........................................................14
PCI Protocol Fundamentals ............................................16
FIFO Memories and Control ............................................17
PCI Bus Pin Information ..................................................18
PCI Bus Core Detailed Description Dual Port ....................21
Embedded Core/FPGA Interface Signal Descriptions ....21
Embedded Core/FPGA Interface Signal Locations .........27
Embedded Core Bit Stream Configurable Options .........32
Understanding FIFO Packing/Unpacking ........................33
Embedded Core/FPGA Interface Operation ...................34
Embedded Core/FPGA Interface Operation Summary ...35
Master (FPGA Initiated) Write .........................................36
Master (FPGA Initiated) Read .........................................42
Target (PCI Bus Initiated) Write ......................................49
Target (PCI Bus Initiated) Read ......................................58
PCI Bus Core Detailed Description Quad Port ...................70
Embedded Core/FPGA Interface Signal Descriptions ....70
Embedded Core/FPGA Interface Signal Locations .........76
Embedded Core Bit Stream Configurable Options .........83
Understanding FIFO Packing/Unpacking ........................84
Embedded Core/FPGA Interface Operation ...................86
Embedded Core/FPGA Interface Operation Summary ...87
Master (FPGA Initiated) Write .........................................88
Master (FPGA Initiated) Read .........................................94
Target (PCI Bus Initiated) Write ....................................101
Target (PCI Bus Initiated) Read ....................................110
Configuration Space of the PCI Core ...............................123
PCI Bus Configuration Space Organization ..................123
2
FPSC Configuration ......................................................... 126
Configuration via PCI Bus ............................................. 126
Readback via PCI interface .......................................... 127
Interaction Among Configuration Modes ...................... 127
Clocking Options at FPGA/Core Boundary ..................... 128
PCI Clock as System Clock .......................................... 128
Local Clock as System Clock ....................................... 128
FPGA Configuration Data Format ................................... 130
Using ORCA Foundry to Generate Configuration
RAM Data ................................................................... 130
FPGA Configuration Data Frame .................................. 130
Bit Stream Error Checking ............................................... 132
FPGA Configuration Modes ............................................. 132
Powerup Sequencing for Series OR3LP26B Device ....... 133
Absolute Maximum Ratings ............................................. 133
Recommended Operating Conditions ............................. 134
Electrical Characteristics ................................................. 135
Timing Characteristics ..................................................... 136
Description .................................................................... 136
Clock Timing ................................................................. 137
Input/Output Buffer Measurement Conditions ................. 148
Output Buffer Characteristics .......................................... 149
Estimating Power Dissipation .......................................... 150
Pin Information ................................................................ 151
Package Compatibility .................................................. 154
Package Thermal Characteristics Summary ................... 178
ΘJA ............................................................................... 178
ψJC ............................................................................... 178
ΘJC ............................................................................... 178
ΘJB ............................................................................... 178
FPGA Maximum Junction Temperature ....................... 178
Package Coplanarity ....................................................... 179
Package Parasitics .......................................................... 180
Package Outline Diagrams .............................................. 181
Terms and Definitions ................................................... 181
352-Pin PBGA .............................................................. 182
680-Pin PBGA .............................................................. 183
Ordering Information ........................................................ 184
Figures
Figure 1. ORCA OR3LP26B PCI FPSC
Block Diagram...............................................................13
Figure 2. Master Write Single (FPGA Bus, Dual-Port).....38
Figure 3. Master Write Single (PCI Bus, 64-Bit) ..............39
Figure 4. Master Write 32-Byte Burst
(FPGA Bus, Dual-Port) .................................................40
Figure 5. Master Write 32-Byte Burst (PCI Bus, 64-Bit) ..41
Figure 6. Master Read Single (FPGA Bus, Dual-Port,
Specified Burst Length, 64-Bit Address).......................44
Figure 7. Master Read Single (PCI Bus, 64-Bit) ..............45
Figure 8. Master Read 32-Byte Burst (FPGA Bus,
Dual-Port, Burst Length, and 64-Bit Address) ..............46
Figure 9. Master Read 32-Byte Burst
(PCI Bus, 64-Bit)...........................................................47
Lucent Technologies Inc.









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OR3LP26B Даташит, Описание, Даташиты
Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Contents
Table of Contents (continued)
Page Contents
Page
Figure 10. Target Configuration Write
(PCI Bus, 64-Bit) ...........................................................52
Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...53
Figure 12. Target Write Memory Single
(PCI Bus, 64-Bit) ...........................................................54
Figure 13. Target Write Single (FPGA Bus, Dual-Port)....55
Figure 14. Target Memory Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................56
Figure 15. Target Write Memory 32-Byte Burst
(FPGA Bus, Dual-Port) .................................................57
Figure 16. Target Configuration Read
(PCI Bus, 64-Bit) ...........................................................61
Figure 17. Target I/O Read, Delayed (PCI Bus, 64-Bit) ...62
Figure 18. Target I/O Read, Not Delayed
(PCI Bus, 64-Bit) ...........................................................63
Figure 19. Target Memory Single Read, Delayed
(PCI Bus, 64-Bit) ...........................................................64
Figure 20. Target Read Single (FPGA Bus, Dual-Port)....65
Figure 21. Target Memory Read Single, Not Delayed
(PCI Bus, 64-Bit) ...........................................................66
Figure 22. Target Memory Read 32-Byte Burst, Delayed
(PCI Bus, 64-Bit) ...........................................................67
Figure 23. Target Read Memory 32-Byte Burst
(FPGA, Dual-Port) ........................................................68
Figure 24. Target Read Memory Burst, No Delayed
(PCI Bus, 32-Bit) ...........................................................69
Figure 25. Master Write Single (PCI Bus, 64-Bit) ............90
Figure 26. Master Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................91
Figure 27. Master Write Single Quadword
(FPGA Bus, Quad-Port, 64-Bit Address) ......................92
Figure 28. Master Write 32-Byte Burst
(FPGA Bus, Quad-Port, 64-Bit Address) ......................93
Figure 29. Master Read Single (PCI Bus, 64-Bit) ............96
Figure 30. Master Read Single Quadword (FPGA Bus,
Quad-Port, Specified Burst Length, 32-Bit Address) ....97
Figure 31. Master Read 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................98
Figure 32. Master Read 32-Byte Burst (FPGA Bus,
Quad-Port, Specified Burst Length, 32-Bit Address) ....99
Figure 33. Target Configuration Write
(PCI Bus, 64-Bit) ...........................................................104
Figure 34. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...105
Figure 35. Target Write Memory Single
(PCI Bus, 64-Bit) ...........................................................106
Figure 36. Target Write Single Quadword
(FPGA Bus, Quad-Port, 64-Bit Address) ......................107
Figure 37. Target Memory Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................108
Figure 38. Target Write Memory 32-Byte Burst
(FPGA Bus, Quad-Port, 32-Bit Address) ......................109
Figure 39. Target Configuration Read
(PCI Bus, 64-Bit) ...........................................................113
Figure 40. Target I/O Read, Delayed
(PCI Bus, 64-Bit) ...........................................................114
Figure 41. Target I/O Read, Not Delayed
(PCI Bus, 64-Bit) .......................................................... 115
Figure 42. Target Memory Single Read, Delayed
(PCI Bus, 64-Bit) .......................................................... 116
Figure 43. Target Read Single (FPGA Bus, Quad-Port,
64-Bit Address)............................................................. 117
Figure 44. Target Memory Read Single, Not Delayed
(PCI Bus, 64-Bit) .......................................................... 118
Figure 45. Target Memory Read 32-Byte Burst, Delayed
(PCI Bus, 64-Bit) .......................................................... 119
Figure 46. Target Read Memory 32-Byte Burst
(FPGA Bus, Quad-Port, 32-Bit Address) ...................... 120
Figure 47. Target Read Memory Burst, No Delayed
(PCI Bus, 32-Bit) .......................................................... 121
Figure 48. FPSC Block Diagram and Clock Network ...... 129
Figure 49. Serial Configuration Data Format—
Autoincrement Mode .................................................... 131
Figure 50. Serial Configuration Data Format—
Explicit Mode ................................................................ 131
Figure 51. ExpressCLK to Output Delay ......................... 138
Figure 52. Fast Clock to Output Delay ............................ 139
Figure 53. System Clock to Output Delay ....................... 140
Figure 54. Input to ExpressCLK Setup/Hold Time .......... 141
Figure 55. Input to Fast Clock Setup/Hold Time.............. 142
Figure 56. Input to System Clock Setup/Hold Time ........ 143
Figure 57. ac Test Loads ................................................. 148
Figure 58. Output Buffer Delays ...................................... 148
Figure 59. Input Buffer Delays......................................... 148
Figure 60. Sinklim (TJ = 25 °C, VDD = 3.3 V) ................. 149
Figure 61. Slewlim (TJ = 25 °C, VDD = 3.3 V) ................ 149
Figure 62. Fast (TJ = 25 °C, VDD = 3.3 V)...................... 149
Figure 63. Sinklim (TJ = 125 °C, VDD = 3.0 V) ............... 149
Figure 64. Slewlim (TJ = 125 °C, VDD = 3.0 V) .............. 149
Figure 65. Fast (TJ = 125 °C, VDD = 3.0 V).................... 149
Figure 66. Package Parasitics ......................................... 180
Tables
Table 1. ORCA OR3LP26B PCI FPSC Solution—
Available FPGA Logic................................................... 1
Table 2. PCI Local Bus Data Rates ................................ 10
Table 3. OR3LP26B Array .............................................. 11
Table 4. PCI Bus Command Descriptions ...................... 14
Table 5. Timing Budgets................................................. 17
Table 6. FIFO Flags Provided to FPGA Application ....... 18
Table 7. PCI Bus Pin Descriptions.................................. 18
Table 8. Embedded Core/FPGA Interface Signals ......... 21
Table 9. OR3LP26B FPGA/PCI Core Interface Signal
Locations ...................................................................... 27
Table 10. Bit Definitions on FPGA/PCI Core Interface ... 30
Table 11. Address Cycle Sequences for Various
Operations ................................................................... 31
Table 12. PCI Core Options Settable via FPGA
Configuration RAM Bits ................................................ 32
Lucent Technologies Inc.
Lucent Technologies Inc.
3










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Номер в каталогеОписаниеПроизводители
OR3LP26BField-Programmable System Chip (FPSC) Embedded Master/Target PCI InterfaceAgere Systems
Agere Systems

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