DataSheet26.com

OR4E4 PDF даташит

Спецификация OR4E4 изготовлена ​​​​«Agere Systems» и имеет функцию, называемую «Field-Programmable Gate Arrays».

Детали детали

Номер произв OR4E4
Описание Field-Programmable Gate Arrays
Производители Agere Systems
логотип Agere Systems логотип 

30 Pages
scroll

No Preview Available !

OR4E4 Даташит, Описание, Даташиты
Preliminary Data Sheet
December 2000
ORCA® Series 4
Field-Programmable Gate Arrays
Programmable Features
s High-performance platform design.
— 0.13 µm seven-level metal technology.
— Internal performance of >250 MHz
(four logic levels).
— I/O performance of >416 MHz for all user I/Os.
— Over 1.5 million usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
— Embedded block RAM (EBR) for onboard stor-
age and buffer needs.
— Built-in system components including an internal
system bus, eight PLLs, and microprocessor
interface.
s Traditional I/O selections.
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability.
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
s New programmable high-speed I/O.
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I & II), HSTL (Class I, III, IV), zero-bus
turn-around (ZBT*), and double data rate (DDR).
— Double-ended: LDVS, bused-LVDS, LVPECL.
— Customer defined: Ability to substitute arbitrary
standard-cell I/O to meet fast moving standards.
s New capability to (de)multiplex I/O signals.
— New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
— Used to implement emerging RapidIOback-
plane interface specification.
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 104 MHz internal to 416 MHz I/O).
s Enhanced twin-quad programmable function unit
(PFU).
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic
carry/borrow operations.
* ZBT is a trademark of Integrated Device Technologies Inc.
RapidIO is a trademark of Motorola, Inc.
Table 1. ORCA Series 4—Available FPGA Logic
Device Columns Rows
OR4E2
OR4E4
OR4E6
OR4E10
OR4E14
26
36
46
60
70
24
36
44
56
66
PFUs
624
1296
2024
3360
4620
User I/O
400
576
720
928
1088
LUTs
4992
10368
16,192
26,880
36,960
EBR
Blocks
8
12
16
20
24
EBR Bits (k)
Usable
Gates (k)
74 260—470
111 400—720
148 530—970
185 740—1350
222 930—1700
† The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic,
CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or
512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates
are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are con-
servatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with ORCA Series 2/3.









No Preview Available !

OR4E4 Даташит, Описание, Даташиты
ORCA Series 4 FPGAs
Preliminary Data Sheet
December 2000
Table of Contents
Contents
Page Contents
Page
Programmable Features............................................. 1
System Features .........................................................4
Product Description .....................................................6
Architecture Overview .............................................6
Programmable Logic Cells ..........................................7
Programmable Function Unit ...................................8
Look-Up Table Operating Modes ..........................11
Supplemental Logic and Interconnect Cell ............21
PLC Latches/Flip-Flops .........................................25
Embedded Block RAM ..............................................27
EBR Features ........................................................27
Routing Resources ...................................................31
Clock Distribution Network ........................................31
Primary Clock Nets ................................................31
Secondary Clock and Control Nets .......................31
Edge Clock Nets ....................................................31
Programmable Input/Output Cells .............................31
Programmable I/O .................................................31
Inputs .....................................................................34
Special Function Blocks ............................................38
Microprocessor Interface (MPI) .................................48
Embedded System Bus (ESB) ..................................49
Phase-Locked Loops.................................................52
FPGA States of Operation.........................................55
Initialization ............................................................ 56
Configuration .........................................................56
Start-Up .................................................................56
Reconfiguration .....................................................60
Partial Reconfiguration ..........................................60
Other Configuration Options ..................................60
Bit Stream Error Checking .....................................62
FPGA Configuration Modes.......................................62
Master Parallel Mode.............................................63
Master Serial Mode ...............................................64
Asynchronous Peripheral Mode ............................65
Microprocessor Interface Mode .............................66
Slave Serial Mode .................................................70
Slave Parallel Mode...............................................70
Daisy Chaining ......................................................71
Daisy-Chaining with Boundary Scan .....................72
Absolute Maximum Ratings.......................................72
Recommended Operating Conditions .......................73
Electrical Characteristics ...........................................73
Pin Information ..........................................................75
Pin Descriptions.....................................................75
Package Compatibility ...........................................78
Package Thermal Characteristics Summary ...........118
ΘJA ......................................................................118
ψJC ......................................................................118
ΘJC ......................................................................118
ΘJB ......................................................................118
Package Thermal Characteristics............................119
Package Coplanarity ...............................................119
Package Parasitics ..................................................119
Package Outline Diagrams......................................120
Terms and Definitions..........................................120
Package Outline Drawings ......................................121
352-Pin PBGA .....................................................121
432-Pin EBGA .....................................................122
680-Pin PBGAM ..................................................123
Ordering Information................................................124
Figure
Page
Figure 1. Series 4 Top-Level Diagram ........................7
Figure 2. PFU Ports .....................................................9
Figure 3. Simplified PFU Diagram .............................10
Figure 4. Simplified F4 and F5 Logic Modes .............12
Figure 5. Simplified F6 Logic Modes .........................13
Figure 6. MUX 4 x 1...................................................13
Figure 7. MUX 8 x 1...................................................14
Figure 8. Softwired LUT Topology Examples.............15
Figure 9. Ripple Mode ...............................................16
Figure 10. Counter Submode ....................................17
Figure 11. Multiplier Submode...................................18
Figure 12. Memory Mode ..........................................19
Figure 13. Memory Mode Expansion
Example128 x 8 RAM ........................................21
Figure 14. SLIC All Modes Diagram ..........................22
Figure 15. Buffer Mode ..............................................23
Figure 16. Buffer-Buffer-Decoder Mode ....................23
Figure 17. Buffer-Decoder-Buffer Mode ....................24
Figure 18. Buffer-Decoder-Decoder Mode ................24
Figure 19. Decoder Mode..........................................25
Figure 20. Latch/FF Set/Reset Configurations ..........26
Figure 21. EBR Read and Write Cycles
with Write Through ................................................29
Figure 22. Series 4 PIO Image from
ORCA Foundry ......................................................33
Figure 23. ORCA High-Speed I/O Banks ..................36
Figure 24. PIO Shift Register.....................................38
Figure 25. Printed-Circuit Board with Boundary-
Scan Circuitry ........................................................39
Figure 26. Boundary-Scan Interface..........................40
Figure 27. ORCA Series Boundary-Scan
Circuitry Functional Diagram .................................43
Figure 28. TAP Controller State Transition
Diagram .................................................................44
Figure 29. Boundary-Scan Cell .................................45
Figure 30. Instruction Register Scan Timing
Diagram .................................................................46
Figure 31. PLL_VF External Requirements...............53
Figure 32. PLL Naming Scheme ...............................54
2 Lucent Technologies Inc.









No Preview Available !

OR4E4 Даташит, Описание, Даташиты
Preliminary Data Sheet
December 2000
ORCA Series 4 FPGAs
Table of Contents (continued)
Contents
Page Contents
Page
Figure 33. FPGA States of Operation ....................... 55
Figure 34. Initialization/Configuration/Start-Up
Waveforms............................................................. 57
Figure 35. Start-Up Waveforms................................. 59
Figure 36. Serial Configuration Data
FormatAutoincrement Mode .............................. 60
Figure 37. Serial Configuration Data
FormatExplicit Mode .......................................... 60
Figure 38. Master Parallel
Configuration Schematic ....................................... 63
Figure 39. Master Serial Configuration Schematic.... 65
Figure 40. Asynchronous Peripheral Configuration... 66
Figure 41. PowerPC/MPI Configuration Schematic... 67
Figure 42. Configuration Through MPI ...................... 68
Figure 43. Readback Through MPI ........................... 69
Figure 44. Slave Serial Configuration Schematic ...... 70
Figure 45. Slave Parallel Configuration Schematic ... 71
Figure 46. Daisy-Chain Configuration Schematic ..... 72
Figure 47. Package Parasitics ................................. 120
Table
Page
Table 1. ORCA Series 4Available FPGA Logic ....... 1
Table 2. System Performance .................................... 5
Table 3. Look-Up Table Operating Modes ................ 11
Table 4. Control Input Functionality .......................... 11
Table 5. Ripple Mode Equality Comparator
Functions and Outputs .......................................... 18
Table 6. SLIC Modes ................................................ 22
Table 7. Configuration RAM Controlled Latch/
Flip-Flop Operation................................................ 25
Table 8. ORCA Series 4Available
Embedded Block RAM .......................................... 27
Table 9. RAM Signals ............................................... 28
Table 10. FIFO Signals ............................................ 29
Table 11. Constant Multiplier Signals ....................... 30
Table 12. 8 x 8 Multiplier Signals.............................. 30
Table 13. CAM Signals ............................................. 30
Table 14. Series 4 Programmable I/O Standards ..... 32
Table 15. PIO Options .............................................. 35
Table 16. PIO Register Control Signals .................... 35
Table 17. PIO Logic Options..................................... 36
Table 18. Compatible Mixed I/O Standards .............. 36
Table 19. LVDS I/O Specifications........................... 37
Table 20. LVDS Termination Pin ............................. 37
Table 21. Dedicated Temperature Sensing.............. 39
Table 22. Boundary-Scan Instructions ..................... 40
Table 23. Series 4E Boundary-Scan
Vendor-ID Codes................................................... 41
Table 24. TAP Controller Input/Outputs ................... 43
Table 25. Readback Options .................................... 46
Table 26. MPC 860 to ORCA MPI Interconnection .. 48
Table 27. Embedded System Bus/MPI Registers..... 50
Table 28. Interrupt Register Space Assignments ..... 50
Table 29. Status Register Space Assignments ........ 51
Table 30. Command Register Space Assignments .. 51
Table 31. PPLL Specifications.................................. 52
Table 32. DPLL DS-1/E-1 Specifications.................. 53
Table 33. Dedicated Pin Per Package ...................... 53
Table 34. STS-3/STM-1 DPLL Specifications........... 54
Table 35. Phase-Lock Loops Index .......................... 54
Table 36A. Configuration Frame Format
and Contents ......................................................... 61
Table 36B. Configuration Frame Format
and Contents for Embedded Block RAM............... 61
Table 37. Configuration Frame Size ......................... 62
Table 38. Configuration Modes................................. 63
Table 39. Absolute Maximum Ratings ...................... 73
Table 40. Recommended Operating Conditions....... 73
Table 41. Electrical Characteristics .......................... 73
Table 42. Pin Descriptions........................................ 75
Table 43. ORCA I/Os Summary ............................... 78
Table 44. 352-Pin PBGA Pinout ............................... 79
Table 45. 432-Pin EBGA .......................................... 89
Table 46. 680-Pin PBGAM Pinout ............................ 99
Table 47. ORCA Series 4 FPGAs Plastic
Package Thermal Guidelines .............................. 119
Table 48. ORCA Series 4 FPGAs
Package Parasitics .............................................. 119
Table 49. Series 4 Package Matrix
(Speed Grades)................................................... 124
Table 50. Package Options..................................... 124
Lucent Technologies Inc.
3










Скачать PDF:

[ OR4E4.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
OR4E10Field-Programmable Gate ArraysAgere Systems
Agere Systems
OR4E2Field-Programmable Gate ArraysAgere Systems
Agere Systems
OR4E4Field-Programmable Gate ArraysAgere Systems
Agere Systems
OR4E6Field-Programmable Gate ArraysAgere Systems
Agere Systems

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск