DataSheet26.com

ORLI10G PDF даташит

Спецификация ORLI10G изготовлена ​​​​«Agere Systems» и имеет функцию, называемую «Quad 2.5 Gbits/s 10 Gbits/s / and 12.5 Gbits/s Line Interface FPSC».

Детали детали

Номер произв ORLI10G
Описание Quad 2.5 Gbits/s 10 Gbits/s / and 12.5 Gbits/s Line Interface FPSC
Производители Agere Systems
логотип Agere Systems логотип 

30 Pages
scroll

No Preview Available !

ORLI10G Даташит, Описание, Даташиты
Data Sheet
October 2001
ORCA® ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Introduction
Agere Systems Inc. has developed a new ORCA
Series 4 based FPSC which combines a high-speed
line interface with a flexible FPGA logic core. Built on
the Series 4 reconfigurable embedded system-on-
chips (SoC) architecture, the ORLI10G consists of an
OIF standard (OIF 99.102.5) compliant XSBI or
OIF-SFI4-01.0 SFI-4, 10 Gbits/s or 12.5 Gbits/s
transmit and 10 Gbits/s or 12.5 Gbits/s receive line
interface. Both transmit and receive interfaces con-
sist of 16-bit LVDS data up to 850 Mbits/s, integrated
transmit and receive programmable PLLs for data
rate conversions between the line-side and system-
side data rates, and a programmable logic interface
at the system end for use with SONET/SDH, Ether-
net, or OTN/digital wrapper with strong FEC system
device data standards. In addition to the embedded
functionality, the device will include up to 400k of
usable FPGA gates. The line interface includes logic
to divide the data rate down to 212 MHz or less
(1/4 line rate) or 106 MHz or less (1/8 line rate) for
transfer to the FPGA logic. The ORLI10G is designed
to connect directly to Agere’s 10 Gbits/s TTRN0110G
MUX and TRCV0110G deMUX or Agere’s
12.5 Gbits/s TTRN0126 MUX and TRCV01126
deMUX on the line side, as well as other industry-
standard devices. The programmable logic interface
on the system side allows for direct connection to a
10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH
framer/data engine, or a 10 Gbits/s/12.5 Gbits/s digi-
tal wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the
physical coding sublayer (PCS), interfaces to the
physical media attachment (PMA), and connects to
the system interface (host or switch) for the proposed
IEEE ® 802.3ae 10 Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable
device for 10G/s data solutions. It can be used as the
interface between the line interface and the system
interface in a variety of emerging networks, including
10 Gbits/s SONET/SDH (OC-192/STM-48),
10 Gbits/s optical transport networks (OTN) using
digital wrapper and strong FEC, or 10 Gbits/s Ether-
net. Other functions include use in Quad OC-48/
STM-16 SONET/SDH systems, interfaces between
Quad OC-48/STM-16 and OC-192/STM-64 compo-
nents, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is
received at the line interface and then sent to either a
4-bit or 8-bit serial-to-parallel converter. On the trans-
mit interface, either a 4-bit or 8-bit parallel-to-serial
converter is used. Thus, the data rate at the internal
FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for
great flexibility in handling clock rate conversion due
to differing amounts of overhead bits in various sys-
tem data standards. For example, the ORLI10G can
divide down the STS-192/STM-64 SONET/SDH data
line rate of 622 MHz by 4 to synchronize with a
155 MHz system clock, or the 12.5 Gbits/s Super-
FEC data line rate of 781 MHz can be divided by 8 to
98 MHz system clock or by 8 x 4/5 to provide a
78 MHz system data rate.
Table 1. ORCA ORLI10G—Available FPGA Logic
Device
ORLI10G
PFU
Rows
36
PFU
Columns
36
Total
PFUs
1296
User I/Os* LUTs
432 10,368
EBR
Blocks
12
EBR Bits
(k)
111
Usable
Gates (k)
380—800
* 192 user I/Os for the 416 PBGAM package and 316 user I/Os for the 680 PBGAM package are available out of the 432 possible user
I/Os.
Note: The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate
count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU).
Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used
as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded
block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25k gates. 7k gates are used for each PLL and
50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in
the gate count calculations.









No Preview Available !

ORLI10G Даташит, Описание, Даташиты
ORCA ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet
October 2001
Table of Contents
Contents
Page Contents
Page
Introduction ..................................................................1
Embedded Function Features .....................................4
Intellectual Property Features......................................4
Programmable Features..............................................4
Programmable Logic System Features .......................6
Description...................................................................7
FPSC Definition ........................................................7
FPSC Overview ........................................................7
FPSC Gate Counting ................................................7
FPGA/Embedded Core Interface ..............................7
ORCA Foundry Development System ......................7
FPSC Design Kit .......................................................8
FPGA Logic Overview...............................................8
PLC Logic .................................................................8
Programmable I/O.....................................................9
Routing......................................................................9
System-Level Features..............................................10
Microprocessor Interface ........................................10
System Bus.............................................................10
Phase-Locked Loops ..............................................10
Embedded Block RAM............................................10
Configuration...........................................................11
Additional Information .............................................11
ORLI10G Overview ...................................................11
Device Layout .........................................................11
10G Mode ...............................................................11
2.5G Mode ..............................................................12
Receive Path Details .................................................15
Line Interface ..........................................................15
DeMUX ...................................................................15
Onboard Receive PLLs...........................................15
Transmit Path Details ................................................17
MUX ........................................................................17
Onboard Transmit PLLs..........................................17
Line Interface ..........................................................17
ORLI10G Demultiplexer (Rx) Detail ..........................19
ORLI10G Multiplexer (Tx) Detail ...............................25
ORLI10G Embedded PLLs........................................31
ORLI10G Embedded Programmable PLLs
Specifications ........................................................... 32
ORLI10G Reset Requirements................................. 32
Line Interface Circuit Specifications ......................... 33
Power Supply Decoupling LC Circuit ..................... 33
XGMII ORCA 4E Receive Analysis .......................... 34
XGMII Considerations ............................................ 34
Absolute Maximum Ratings...................................... 35
Recommended Operating Conditions ...................... 35
Embedded Core LVDS I/O ....................................... 36
LVDS Receiver Buffer Requirements..................... 37
Timing Characteristics .............................................. 38
Receive Input Data Interface.................................. 38
Transmit STS-48/STS-192 (2.5G/10G) Data
Outputs ..................................................................... 39
Input/Output Buffer Measurement Conditions
(Non-LVDS Buffer) ................................................... 40
LVDS Buffer Characteristics..................................... 41
Termination Resistor .............................................. 41
LVDS Driver Buffer Capabilities ............................. 41
Pin Information ......................................................... 42
Package Pinouts .................................................... 47
Package Thermal Characteristics Summary ............ 65
ΘJA ........................................................................ 65
ψJC ........................................................................ 65
ΘJC ........................................................................ 65
ΘJB ........................................................................ 65
FPSC Maximum Junction Temperature ................. 65
Package Thermal Characteristics............................. 66
Heat Sink Vendors for BGA Packages ..................... 66
Package Coplanarity ................................................ 66
Package Parasitics ................................................... 67
Package Outline Diagrams....................................... 68
Terms and Definitions ............................................ 68
416-Pin PBGAM..................................................... 69
680-Pin PBGAM..................................................... 70
Hardware Ordering Information ................................ 71
Software Ordering Information ................................. 71
2 Agere Systems Inc.









No Preview Available !

ORLI10G Даташит, Описание, Даташиты
Data Sheet
October 2001
ORCA ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
List of Figures
Table of Contents (continued)
Page List of Tables
Page
Figure 1. ORCA ORLI10G Block Diagram ...............13
Figure 2. 10G (Single-Channel) and 2.5G
(Quad-Channel) Modes .........................................14
Figure 3. ORLI10G Embedded Core Receive
Path Diagram .........................................................16
Figure 4. ORLI10G Embedded Core Transmit Path
Diagram .................................................................18
Figure 5. Demultiplexer Output Data Structure ........20
Figure 6. Demultiplexer Serial-to-Parallel
ConversionDivide by 8, 10G Mode .....................21
Figure 7. Demultiplexer Serial-to-Parallel
ConversionDivide by 4, 10G Mode .....................22
Figure 8. Demultiplexer Serial-to-Parallel
ConversionDivide by 8, 2.5G Mode ....................23
Figure 9. Demultiplexer Serial-to-Parallel
ConversionDivide by 4, 2.5G Mode ....................24
Figure 10. Multiplexer Input Data Structure ..............26
Figure 11. Multiplexer Parallel-to-Serial
ConversionDivide by 8, 10G Mode .....................27
Figure 12. Multiplexer Parallel-to-Serial
ConversionDivide by 4, 10G Mode .....................28
Figure 13. Multiplexer Parallel-to-Serial
ConversionDivide by 8, 2.5G Mode ....................29
Figure 14. Multiplexer Parallel-to-Serial
ConversionDivide by 4, 2.5G Mode ....................30
Figure 15. ORLI10G Programmable PLL Block
Diagram .................................................................31
Figure 16. Sample Power Supply Filter Network for
Analog LI Power Supply Pins .................................33
Figure 17. Simplified XGMII Block Diagram .............34
Figure 18. Receive Input Data Timing ......................38
Figure 19. Transmit Output Data Timing ..................39
Figure 20. ac Test Loads ..........................................40
Figure 21. Output Buffer Delays ...............................40
Figure 22. Input Buffer Delays ..................................40
Figure 23. LVDS Driver and Receiver and Associated
Internal Components ..............................................41
Figure 24. LVDS Driver and Receiver ......................41
Figure 25. LVDS Driver ............................................41
Figure 26. Package Parasitics ..................................67
Table 1. ORCA ORLI10GAvailable FPGA Logic ... 1
Table 2. Programmable PLL Specifications ............ 32
Table 3. ORLI10G Reset Requirements .................. 32
Table 4. HSTL Input Requirements to FPGA .......... 35
Table 5. Absolute Maximum Ratings ....................... 35
Table 6. Recommended Operating Conditions ....... 35
Table 7. Driver dc Data ............................................ 36
Table 8. Driver ac Data ............................................ 36
Table 9. Driver Power Consumption ........................ 36
Table 10. Receiver ac Data ..................................... 37
Table 11. Receiver Power Consumption ................. 37
Table 12. Receiver dc Data ..................................... 37
Table 13. LVDS Operating Parameters ................... 37
Table 14. Receive Data Input Timing ...................... 38
Table 15. Transmit Data Output Timing .................. 39
Table 16. FPGA Common-Function Pin
Description ............................................................ 42
Table 17. FPSC Function Pin Description ............... 45
Table 18. Embedded Core/FPGA Interface Signal
Description ............................................................ 46
Table 19. ORCA Programmable I/Os Summary ...... 47
Table 20. PBGA Pinout Table ................................. 48
Table 21. ORCA ORLI10G Plastic Package
Thermal Guidelines ............................................... 66
Table 22. Heat Sink Vendors ................................... 66
Table 23. . ORCA ORLI10G Package Parasitics .... 67
Table 24. Device Type Options ............................... 71
Table 25. Temperature Options ............................... 71
Table 26. Package Options ..................................... 71
Table 27. Package Matrix (Speed Grade) ............... 71
Agere Systems Inc.
3










Скачать PDF:

[ ORLI10G.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
ORLI10GQuad 2.5 Gbits/s 10 Gbits/s / and 12.5 Gbits/s Line Interface FPSCAgere Systems
Agere Systems

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск